AD1981BJSTZ Analog Devices Inc, AD1981BJSTZ Datasheet - Page 29

• Manufacturer Part Number: AD1981BJSTZ
• Description: IC CODEC STEREO MICPREAMP 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1981BJSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3/4.5V
• Single Supply Voltage (max): 3.47/5.5V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL CONFIGURATION REGISTER
Index 0x74
Reg No.
0x74
Table 42.
Bit
SPLNK
SPDZ
SPAL
INTS
CHEN
REGM0
REGM1
REGM2
SLOT16
MISCELLANEOUS CONTROL BIT REGISTER
Index 0x76
Reg
No.
0x76
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 43.
Bit
MBG [1:0]
All registers are not shown, and bits containing an X are assumed to be reserved.
This register is not reset when the reset register (Register 0x00) is written.
Name
Misc
Control
Bit
Name
Serial
Config
Mnemonic
SPDIF Link
SPDIF DACZ
SPDIF ADC Loop-
Around
Interrupt Mode Select
Chain Enable
Master Codec Register
Mask
Slave 1 Codec Register
Mask
Slave 2 Codec Register
Mask
Enable 16-Bit Slot Mode
Mnemonic
MIC Boost Gain Change
Register
D15
DACZ
D15
SLOT16
D14
X
D14
REGM2
D13
MSPLT
D13
REGM1
D12
LODIS
Function
This bit enables the SPDIF to link with the DAC for data requests.
0 = SPDIF and DAC are not linked.
1 = SPDIF and DAC are linked and receive the same data requests (reset default).
0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default).
1 = Forces midscale sample out the SPDIF stream if FIFO underruns.
0 = SPDIF transmitter is connected to the ac-link stream (reset default).
1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link.
This bit selects the JS interrupt implementation path.
0 = Bit 0 Slot 12 (modem interrupt).
1 = Slot 6 valid bit (MIC ADC interrupt).
This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0 = Disable chaining (reset default).
1 = Enable chaining into ID0 pin.
Slot 16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for
DSP serial port interfacing.
Function
These two bits allow changing the MIC preamp gain from the nominal 20 dB gain.
This gain setting takes effect only while Bit D6 (M20) on the MIC volume register (0x0E) is set to 1;
otherwise, the MIC boost block has a gain of 0 dB.
00 = 20 dB gain (reset default).
01 = 10 dB gain.
10 = 30 dB gain.
11 = Reserved.
D11
DAM
D12
REGM0
D10
X
D11
X
D9
FMXE
Rev. C | Page 29 of 32
D10
X
D8
X
D9
X
D7
MADPD
D8
CHEN
D6
2CMIC
D7
X
D6
X
D5
X
D5
X
D4
MADST
D4
INTS
D3
VREFH
D3
X
D2
SPAL
D2
VREFD
D1
SPDZ
MBG1
D1
D0
SPLNK
AD1981B
D0
MBG0
Default
0x7001
Default
0x0000