AD1981BJSTZ Analog Devices Inc, AD1981BJSTZ Datasheet - Page 22

• Manufacturer Part Number: AD1981BJSTZ
• Description: IC CODEC STEREO MICPREAMP 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1981BJSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3/4.5V
• Single Supply Voltage (max): 3.47/5.5V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1981B
EXTENDED AUDIO ID REGISTER
Index 0x28
Reg No.
0x28
Table 30.
Bit
VRAS
SPDIF
DSA [1:0]
AMAP
REVC [1:0]
IDC [1:0]
EXTENDED AUDIO STATUS AND CONTROL REGISTER
Index 0x2A
Reg
No.
0x2A
Table 31.
Bit
VRA
SPDIF
SPSA [1:0]
extended audio features are supported.
The extended audio status and control register is a read/write register that provides status and control of the extended audio features.
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates that one or more of the
All registers are not shown, and bits containing an X are assumed to be reserved.
All registers are not shown, and bits containing an X are assumed to be reserved.
Name
Ext’d Audio
Stat/Ctrl
Name
Ext’d Audio ID
Mnemonic
Variable Rate Audio
(Read/Write)
SPDIF Transmitter
Subsystem Enable/Disable
Bit (Read/Write)
SPDIF Slot Assignment Bits
(Read/Write)
Mnemonic
Variable Rate PCM Audio
Support (Read-Only)
SPDIF Support (Read-Only)
DAC Slot Assignments
(Read/Write)
Slot DAC Mappings Based
on Codec ID (Read-Only)
AC ’97 Revision Compliance
Indicates Codec
Configuration (Read-Only)
D15
IDC1
D15
VFORCE
D14
IDC0
D14
X
D13
X
D13
X
Function
VRA = 0 sets the fixed sample rate audio to 48 kHz (reset default).
VRA = 1 enables variable rate audio mode (enables sample rate registers and SLOTREQ
signaling).
SPDIF = 1 enables the SPDIF transmitter.
SPDIF = 0 disables the SPDIF transmitter (default).
This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can
be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec
transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic is
disabled and this bit returns a low, indicating that the SPDIF transmitter is not available. This bit
must always be read back to verify that the SPDIF transmitter is enabled.
These bits control the SPDIF slot assignment and respective defaults, depending on the codec
ID configuration.
D12
X
Function
This bit returns a 1 when Read To indicates that the variable rate PCM audio is supported.
This bit returns a 1 when Read To indicates that the SPDIF transmitter is supported (IEC958).
This bit is also used to validate that the SPDIF transmitter output is enabled. The SPDIF bit can
be set high only if the SPDIF pin (Pin 48) is pulled down at power-up, enabling the codec
transmitter logic. If the SPDIF pin is floating or pulled high at power-up, the transmitter logic
is disabled; therefore, this bit returns a low, indicating that the SPDIF transmitter is not
available. This bit must always be read back to verify that the SPDIF transmitter is actually
enabled.
Reset default = 00.
00 DACs 1, 2 = 3 and 4.
01 DACs 1, 2 = 7 and 8.
10 DACs 1, 2 = 6 and 9.
11 Reserved.
This bit returns a 1 when read to indicate that slot/DAC mappings based on the codec ID are
supported.
REVC [1:0] = 01 indicates that the codec is AC ’97 revision 2.2 compliant (read-only).
00 = Primary.
01, 10, 11 = Secondary.
D12
X
D11
REVC1
D11
X
D10
REVC0
Rev. C | Page 22 of 32
D10
SPCV
D9
AMAP
D9
X
D8
X
D8
X
D7
X
D7
X
D6
X
D6
X
D5
SPSA1
D5
DSA1
D4
DSA0
D4
SPSA0
D3
X
D3
X
D2
SPDIF
D2
SPDIF
D1
X
D1
X
D0
VRAS
D0
VRA
Default
0xX605
Default
0x0000