AD1981BJSTZ Analog Devices Inc, AD1981BJSTZ Datasheet - Page 13

• Manufacturer Part Number: AD1981BJSTZ
• Description: IC CODEC STEREO MICPREAMP 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1981BJSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3/4.5V
• Single Supply Voltage (max): 3.47/5.5V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CONTROL REGISTER DETAILS
RESET REGISTER
Index 0x00
Reg No.
0x00
SE[4:0] Stereo Enhancement. The AD1981B does not provide hardware 3D stereo enhancement (all bits are 0s).
ID[9:0] Identify Capability. The ID decodes the capabilities of AD1981B based on the functions listed in Table 9.
Table 9. ID Bits
Bit
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
MASTER VOLUME REGISTER
Index 0x02
This register controls the Line_Out volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits,
generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to maintain compatibility
whenever the D5 or D13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. On readback,
all lower five bits read 1s whenever these bits are set to 1. Refer to Table 12 for examples.
Reg No.
0x02
1
Table 10.
Bit
RMV [4:0]
RM
LMV [4:0]
MM
Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.
For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved.
X is a wild card and has no effect on the value.
Writing any value to this register performs a register reset that causes all registers to revert to their default values (except 0x74, which forces the serial configuration).
Function
Dedicated MIC PCM in Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
Name
Master
Volume
Name
Reset
Mnemonic
Right Master Volume
Control
Right-Channel Mute
Left Master Volume
Control
Master Volume Mute
D15
MM
D15
X
D14
X
D14
SE4
D13
X
D13
SE3
Function
The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
attenuation of 46.5 dB.
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from the
MM bit. Otherwise, this bit always reads 0 and has no effect when set to 1.
The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum
attenuation of 46.5 dB.
When this bit is set to 1, both the left and right channels are muted, unless the MSPLT bit in
Register 0x76 is set to 1, in which case this mute bit affects only the left channel.
D12
LMV4
D12
SE2
D11
LMV3
AD1981B
0
0
0
0
1
0
0
1
0
0
D11
SE1
D10
LMV2
D10
SE0
Rev. C | Page 13 of 32
D9
LMV1
D9
ID9
D8
LMV0
D8
ID8
D7
RM
D7
ID7
1
D6
X
ID6
D6
D5
X
D5
ID5
D4
RMV4
D4
ID4
D3
RMV3
D3
ID3
D2
RMV2
D2
ID2
D1
RMV1
D1
ID1
ID0
D0
D0
RMV0
AD1981B
Default
0x0090
Default
0x8000