IDTSTAC9753AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1XR Datasheet - Page 85

• Manufacturer Part Number: IDTSTAC9753AXNAED1XR
• Description: IC CODEC AC'97 MIC/JACK 32-QFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753AXNAED1XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753AXNAED1XR

8. LOW POWER MODES
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
The STAC9752A/9753A is capable of operating at reduced power when no activity is required. The
state of power down is controlled by the Powerdown Register (26h). There are seven separate com-
mands of power down. The power down options are listed in Table 28. The first three bits,
PR0..PR2, can be used individually or in combination with each other, and control power distribution
to the ADCs, DACs and Mixer. The last analog power control bit, PR3, affects analog bias and refer-
ence voltages, and can only be used in combination with PR1, PR2, and PR3. PR3 essentially
removes power from all analog sections of the CODEC, and is generally only asserted when the
CODEC will not be needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only.
PR2 and PR3 do not need to be "set" before a PR4, but PR0 and PR1 should be "set" before PR4.
PR5 disables the DSP clock and does not require an external cold reset for recovery. PR6 disables
the headphone driver amplifier for additional analog power saving.
The Figure 22 illustrates one example procedure to do a complete powerdown of STAC9752A/
9753A . From normal operation, sequential writes to the Powerdown Register are performed to
power down STAC9752A/9753A a section at a time. After everything has been shut off, a final write
(of PR4) can be executed to shut down the AC-Link. The part will remain in sleep mode with all its
registers holding their static values. To wake up, the AC'97 Controller will send an extended pulse on
the sync line, issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The
STAC9752A/9753A can also be woken up with a cold reset. A cold reset will reset all of the registers
to their default states (Paged Registers are semi-exempt). When a section is powered back on, the
Powerdown Control/Status register (index 26h) should be read to verify that the section is ready (sta-
ble) before attempting any operation that requires it.
Normal
Figure 22. Example of STAC9752A/9753A Powerdown/Powerup Flow
GRP Bits
PR0=0 & ADC=1
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR0=1
Ready =1
ADCs off PR0
PCM in ADCs & Input Mux Powerdown
PCM out DACs Powerdown
Analog Mixer powerdown (VREF still on)
Analog Mixer powerdown (VREF off)
Digital Interface (AC-Link) powerdown (BIT CLK forced low)
Digital Clock disable, BIT CLK still on
Powerdown HEADPHONE_OUT
PR1=0 & DAC=1
PR1=1
DACs off PR1
Default
Table 28. Low Power Modes
PR2=0 & ANL=1
85
PR2=1
PR2 or PR3
Analog off
Cold Reset
PR4=1
Function
Digital I/F off
Warm Reset
STAC9752A/9753A
PR4
AC-Link
Shut off
PC AUDIO
V 1.5 1206