IDTSTAC9753AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1XR Datasheet - Page 66

• Manufacturer Part Number: IDTSTAC9753AXNAED1XR
• Description: IC CODEC AC'97 MIC/JACK 32-QFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753AXNAED1XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753AXNAED1XR

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot
in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable
“on-demand” data transfers. If the VRA enable bit is not set, the CODEC will default to 48 KHz trans-
fers and every audio frame will include an active slot request flag and data is transferred every
frame.
For variable sample rate output, the CODEC examines its sample rate control registers, the state of
the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to
determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current
audio input frame for active output slots, which will require data in the next audio output frame.
For variable sample rate input, the tag bit for each input slot indicates whether valid data is present
or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN
(CODEC to controller), the CODEC sets the TAG bit; for SDATA_OUT (controller to CODEC), the
CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. Whenever VRA is
set to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz).
7.1.20.2.
The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the
SPDIF functionality within the STAC9752A/9753A. If the SPDIF is set to a 1, then the function is
enabled. When set to a 0, it is disabled.
7.1.20.3.
The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When
SPCV is a 0, it indicates the system configuration is invalid. When SPCV is a 1, it indicates the sys-
tem configuration is valid.
7.1.20.4.
SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following
details the slot assignment relationship between SPSA1 and SPSA0.
The STAC9752A/9753A are AMAP compliant with the following table.
CODEC
00
01
10
11
ID
2-ch Primary with
SPDIF
2-ch Dock CODEC
with SPDIF
+2-ch Surr w/ SPDIF
+2-ch Cntr/LFE with
SPDIF
SPDIF
SPCV (SPDIF Configuration Valid)
SPSA1, SPSA0 (SPDIF Slot Assignment)
Function
Note:* is the default slot assignment
Slot Assignment
SPSA=00
3 & 4
3 & 4
3 & 4
3 & 4
Table 20. AMAP compliant
66
Slot Assignment
SPSA=01
7 & 8
7 & 8
7 & 8
7 & 8
*
STAC9752A/9753A
Slot Assignment
SPSA=10
6 & 9
6 & 9
6 & 9
6 & 9
*
*
Slot Assignment
SPSA=11
10 & 11
10 & 11
10 & 11
10 & 11
PC AUDIO
V 1.5 1206
*