IDTSTAC9753AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1XR Datasheet - Page 30

• Manufacturer Part Number: IDTSTAC9753AXNAED1XR
• Description: IC CODEC AC'97 MIC/JACK 32-QFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753AXNAED1XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753AXNAED1XR

1.
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
4.6.3.
Secondary CODEC always configures its BIT_CLK pin as an input.
AC-Link. This functionality is typically implemented in modem CODECs that detect ring, Caller ID,
etc.
Note that when the AC-Link is either programmed to the low power mode or shut off completely,
BIT_CLK may stop if the primary CODEC is supplying the clock, which shuts down the AC-Link
clock to the Secondary CODEC
(phone ringing), it must support an independent clocking scheme for any PME# associated logic that
must be kept alive when the AC-Link is down. This includes logic to asynchronously drive
SDATA_IN to a logic high-level, which signals a wake request to the AC‘97 Digital Controller.
CODEC Reset
There are three types of AC‘97 reset:
•
•
•
4.6.3.1.
A cold reset is achieved by asserting RESET# low for the minimum specified time, then subse-
quently de-asserting RESET# high. BIT_CLK and SDATA_IN will be activated, or re-activated as the
case may be, and all AC‘97 control registers will be initialized to their default power on reset values.
RESET# is an asynchronous AC‘97 input.
4.6.3.2.
A warm AC‘97 reset will re-activate the AC-Link without altering the current AC‘97 register values. A
warm reset is signaled by driving SYNC high for a minimum of 1 s in the absence of BIT_CLK.
Within normal audio frames SYNC is a synchronous AC‘97 input. However, in the absence of
BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to
AC‘97.
AC‘97 MUST NOT respond with the activation of BIT_CLK until SYNC has been sampled low again
by AC‘97. This will preclude the false detection of a new audio frame.
4.6.3.3.
Most registers in an AC97 device can be restored to their default values by performing a write (any
value) to the Reset Register, 00h.
a cold reset where all AC‘97 logic (most registers included) is initialized to its default state
a warm reset where the contents of the AC‘97 register set are left unaltered
a register reset which only initializes the AC‘97 registers to their default states
Cold AC‘97 Reset
Warm AC‘97 Reset
Register AC‘97 Reset
1
. In order for a Secondary CODEC to react to an external event
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STAC9752A/9753A
PC AUDIO
V 1.5 1206