IDTSTAC9753AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1XR Datasheet - Page 40

• Manufacturer Part Number: IDTSTAC9753AXNAED1XR
• Description: IC CODEC AC'97 MIC/JACK 32-QFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753AXNAED1XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753AXNAED1XR

1. There are several subsections within an AC‘97 CODEC that can independently go busy/ready. It is the responsibility
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
of the AC’97 Controller to probe more deeply into the AC‘97 CODEC’s register file to determine which subsections
are actually ready.
5.4.2.
before attempting any register writes, or attempting to enable any audio stream, to avoid undesirable
audio artifacts.
Prior to any attempts at putting an AC‘97 CODEC into operation, the AC‘97 Controller should poll the
first bit in the AC-Link input frame (SDATA_IN slot 0, bit 15) for an indication that CODEC has gone
“CODEC Ready”. Once an AC‘97 CODEC is sampled “CODEC Ready”
tions sampled by the AC‘97 Controller indicate which of the corresponding 12 time slots are
assigned to input data streams, and that they contain valid data.
Slot 1: Status Address Port / SLOTREQ Signaling Bits
5.4.2.1.
The status port is used to monitor status for the STAC9752A/9753A functions including, but not lim-
ited to, mixer settings and power management. AC-Link input frame slot 1’s stream echoes the con-
trol register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1
and 2 had been tagged “valid” by the AC‘97 CODEC during slot 0.
The first bit (MSB) generated by AC‘97 is always stuffed with a 0. The following 7 bit positions com-
municate the associated control register address, the next 10 bits support AC‘97’s variable sample
rate signaling protocol, and the trailing 2 bit positions are stuffed with 0s by AC‘97.
5.4.2.2.
AC-Link input frame Slot #1, the Status Address Port, now delivers CODEC control register read
address and variable sample rate slot request flags for all output slots. Ten of the formerly reserved
least significant bits have been defined as data request flags for output slots 3-12.
The AC-Link input frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY
indicates valid Status Address Port data (Control Register Index). The CODEC should only set
SDATA_IN tag bits for Slot 1 (Address) and Slot 2 (Data) to 1 when returning valid data from a previ-
ous register read. They should otherwise be set to 0. SLOTREQ bits have validity independent of the
Slot 1 tag bit.
18:12
11:2
Bit
1:0
19
Status Address Port
SLOTREQ signaling bits
Control Register Index
Description
SLOTREQ
Reserved
Reserved
Table 9. Status Address Port Bit Assignments
40
Echo of register index for which data is being returned
See Section5.4.2.2: page40
STAC9752A/9753A
Stuffed with 0s
Stuffed with 0s
Comments
1
then the next 12 bit posi-
PC AUDIO
V 1.5 1206