CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 33

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

DS686PP1
6.2
MAP(3:0) - Memory Address Pointer
INCR
7
0
I²C
In I²C Mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with
the clock to data relationship as shown in
partial chip address and should be tied to VLC or DGND as required. The upper 4 bits of the 7-bit address
field must be 1001. To communicate with the CS4270, the three lower bits of the chip address field should
match the setting on the AD0, AD1, and AD2 pins. The eighth bit of the address byte is the R/W bit (high for
a read, low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be
read or written. If the operation is a write, the MAP is then followed by the data to be written. If the operation
is a read, then the contents of the register pointed to by the MAP will be output after the chip address.
The CS4270 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the
MAP will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte
is written, allowing block reads or writes of successive registers.
Default = ‘0000’.
®
Mode
Reserved
SDA
SCL
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
6
0
Start
1001
Reserved
5
0
AD2
Figure 22. Control Port Timing,
ADDR
-
AD0
INCR - Auto MAP Increment Enable
Table 7. Memory Address Pointer
Reserved
R/W
4
0
Figure
Default = ‘0’.
0 - Disabled
ACK
1 - Enabled
22. There is no CS pin. Pins AD0, AD1, and AD2 form the
DATA
1-8
MAP3
3
0
Note 1
ACK
I²C
Mode
DATA
1-8
MAP2
2
0
ACK
Stop
MAP1
1
0
CS4270
MAP0
0
0
33