CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 25

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

DS686PP1
5.2.3 System Clocking
5.2.4 Clock Ratio Selection
Single-Speed
Double-Speed
Quad-Speed
Single-Speed
The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three
speed modes as shown in
In Control Port Master Mode, the user must configure the mode bits (MCLK Freq<2:0>) to set the speed
mode and select the appropriate clock ratios. Depending on whether the CS4270 is in Master or Slave
Mode, different MCLK/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Control
Port Register Bits are shown in
MCLK/LRCK
MCLK/LRCK
1024
1024
256
384
512
768
128
192
256
384
512
128
192
256
256
384
512
768
64
96
Single-Speed
Double-Speed
Quad-Speed
Table
Table 5. Clock Ratios - Control Port Mode
Table
Mode
4.
32, 48, 64, 96, 128
32, 48, 64, 96, 128
Table 4. Speed Modes
SCLK/LRCK
SCLK/LRCK
5,
32, 64, 128
32, 64, 128
32, 64, 128
Master Mode
Table 9
Slave Mode
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
Sampling Frequency
and
100-216 kHz
50-108 kHz
Section 8.3 on page
4-54 kHz
LRCK
LRCK
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Freq<2>
Freq<2>
MCLK
MCLK
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
36.
Freq<1>
Freq<1>
MCLK
MCLK
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
CS4270
Freq<0>
Freq<0>
MCLK
MCLK
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
25