CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet
CS4270-DZZ
Specifications of CS4270-DZZ
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CS4270-DZZ Summary of contents
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... Filter ADC High Pass Digital Filter Filter ADC High Pass Digital Filter Filter Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved) CS4270 Conversion VA 3 Internal Voltage Reference External Mute Mute Signals Control Switch-Cap Analog Out A DAC and ...
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... A used in a wide variety of applications where one audio channel and one DC measurement channel is desired. The CS4270 is available in a 24-pin TSSOP package (-10° to +70° C). The CDB4270 Customer Demonstra- tion board is also available for device evaluation and implementation suggestions. Please refer to Information” ...
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... Transition Control - Address 05h ................................................................................................... 35 8.6 Mute Control - Address 06h .......................................................................................................... 36 8.7 DAC Channel A Volume Control - Address 07h ............................................................................ 36 8.8 DAC Channel B Volume Control - Address 08h ............................................................................ 37 9. FILTER PLOTS ................................................................................................................................ 38 10. PARAMETER DEFINITIONS .............................................................................................................. 42 11. PACKAGE DIMENSIONS .................................................................................................................. 43 THERMAL CHARACTERISTICS .......................................................................................................... 43 12. ORDERING INFORMATION .............................................................................................................. 44 13. REVISION HISTORY .......................................................................................................................... 44 DS686F1 CS4270 3 ...
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... Mute Control (Output) - Mute control signal used to control the state of the optional external analog muting MUTEB 24 circuitry. See Section 5.6 on page AOUTA 22 Analog Audio Output (Output) - Analog outputs from the DAC. AOUTB Pin Description 27. CS4270 MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST AD2 DS686F1 ...
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... Mute Control (Output) - Mute control signal used to control the state of the optional external analog mut- MUTEB 24 ing circuitry. See AOUTA 22 Analog Audio Output (Output) - Analog outputs for the DAC. AOUTB 23 DS686F1 Pin Description Section 5.6 on page 27. CS4270 MUTEB AOUTB AOUTA MUTEA AGND VA FILT+ VQ AINB AINA RST MDIV2 I²S format for the Serial Audio 5 ...
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... Output 3.3 V-5.0 V, CMOS Input - Output 3.3 V-5.0 V, CMOS Output 3.3 V-5.0 V, CMOS Table 1. Digital I/O Pin Power Rails CS4270 Receiver 1.8 V-5.0 V, with hysteresis 1.8 V-5.0 V, with hysteresis 1.8 V-5.0 V 1.8 V-5.0 V 1.8 V-5.0 V 1.8 V-5.0 V 1.8 V-5.0 V 1.8 V-5 ...
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... SCL/CCLK (M0) MUTEA RST AOUTA AOUTB MUTEB VLC DGND 2. In Stand-Alone mode, use pull-down to select Slave Mode pull- select Master Mode. See "Master/Slave Mode Selection." Figure 1. CS4270 Typical Connection Diagram CS4270 +3 +3 GND k ( Audio Data Processor SDIN Timing Logic SCLK ...
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... Symbol Min Analog VA -0.3 VD -0.3 Digital VLC -0.3 Serial Control Port (Note AGND-0.7 IN Serial Control Port V -0.3 IND-C V -0.3 Digital IND -65 stg CS4270 Nom Max Units 5.0 5.25 V 3.3 5.25 V 3.3 5.25 V C - +85 Typ Max Units - +6 +6 +6.0 V VA+0 ...
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... Typ A-weighted 99 unweighted 96 DR A-weighted 90 unweighted - -60 dB THD - - Symbol Min (1 kHz -100 0.6• OUTmax OUT 125 100 V out 2.5 3 CS4270 = +25° C; Full-Scale Out k (see Figure 3.3 V Max Min Typ Max 105 - 97 103 - 102 - 94 100 - -87 -83 - -83 -79 - - -40 - -85 -81 - -81 -77 - ...
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... kHz - Fs = 44.1 kHz - kHz - to -0.1 dB corner corner 0 -.15 .5770 (Note 6) 55 tgd - to -0.1 dB corner corner 0 -.12 0.7 (Note 6) 51 tgd - Section 9. “Filter Plots” on page CS4270 Typ Max Unit - . .4992 10/ +1.5/+ +.05/-. -.2/-. . .501 ...
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... Min kHz A-weighted 99 unweighted 96 (Note THD kHz A-weighted 99 unweighted 96 - (Note -20 dB THD 192 kHz A-weighted 99 unweighted 96 - (Note -20 dB THD Min - - -3 - 0.53*VA - CS4270 = 25° C; 997 Hz Input 3.3 V Typ Max Min Typ Max 105 - 96 102 - 102 - -95 -90 - -92 -87 - - -39 - 105 - 96 102 - 102 - -95 -90 - ...
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... The filter frequency response scales precisely with Fs. 11. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. 12 (Note 9) Symbol (Note 10) (Note 10 (Note 10) (Note 10 (Note 10) (Note 10 (Note 11) (Note 11) Section 9. “Filter Plots” on page 38. See CS4270 Min Typ Max Unit 0.035 dB 0. ...
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... PSRR - FILT Symbol Serial Audio Interface V IH Serial Control Port Serial Audio Interface V IL Serial Control Port Serial Audio Interface V Serial Control Port OH MUTEA, MUTEB CS4270 Typ Max Unit 224 270 mW 345 400 mW W 365 - VA/2 ...
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... Single-Speed Mode t sclkw Double-Speed Mode t sclkw Quad-Speed Mode t sclkw t slrd t stp t hld t sdis t sdih Table 9 on page 33, and Table 13 on page 5 and 7. CS4270 Min Typ Max 108 100 - 216 1.024 - 55.296 1.024 - 55.296 ----------------- - - ...
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... SDOUT Figure 5. Slave Mode, Left-Justified SAI LRCK input SCLK input t sdo SDOUT MSB-1 MSB-2 MSB-3 t sclkw t sdis Figure 8. Master and Slave Mode, SCLK/SDIN CS4270 t slrd t sclkh t sclkl t stp t hld MSB t slrd t sclkh t sclkl t stp t hld Figure 7. Slave Mode, I²S SAI t sdih ...
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... Channel A - Left SCLK SDATA - LSB MSB 32 clocks Figure 11. Format Right-Justified 16-Bit or 24-Bit Data (Serial Control Port Mode Only LSB MSB + LSB MSB - I²S Figure 10. Format 24-Bit Data - LSB CS4270 Channel B - Right + LSB Channel B - Right + LSB Channel B - Right Right Channel - MSB -6 DS686F1 LSB ...
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... Figure 12. Software Mode Timing - I²C Format DS686F1 = Symbol f scl t irs t buf t hdst t low t high t sust t hdd t sud susp t ack t high t t sud t ack hdd CS4270 Min Max Unit - 100 kHz 500 - ns 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ µs 250 - µs - 300 ns 4 ...
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... CDIN CDOUT pF. L Symbol f sclk t srs t spi t csh t css t scl t sch t dsu (Note 21) t scdov t cscdo t css t scl t sch dsu scdov t scdov Figure 13. SPI Control Port Timing CS4270 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 ns - 100 ns - 100 all other times. ...
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... Master Mode is accessed by placing a 47 k pull- the SDOUT (M/S) pin. Configuration of clock ratios in each of these modes is outlined in 5.1.3 System Clocking The CS4270 operates at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes, as shown in DS686F1 Speed Mode Approximate Delay Time 21 ...
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... Plots of the data are contained in 5.1.6 High-Pass Filter At the system level, the input circuitry driving the CS4270 may generate a small DC offset into the ADC. The CS4270 includes one high-pass filter per channel after the decimator to remove any DC offset, which 20 Table 4. ‘ ...
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... Single-Speed Mode. In Stand-Alone Master Mode, the CS4270 must be set to the proper mode via the mode pins, M1 and M0. In Slave Mode, the CS4270 auto-detects Speed Mode and the M0 pin becomes De-emphasis select. Stand-alone definitions of the mode pins in Master Mode are shown in Table 5 ...
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... Changes to these bits should only be done while the PDN bit is set. Depending on whether the CS4270 is in Master or Slave Mode, different MCLK/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Serial Control Port Register Bits are shown ...
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... ADC is routed to the input of the DAC. This mode may be activated by setting the DIG_LOOPBK bit in the ADC and DAC Control register (04h). When this bit is set, the CS4270 ignores the status of the DAC_DIF(4:3) bits in register 04h. Any changes made to the DAC_DIF(4:3) bits while the DIG_LOOPBK bit is set will have no impact on operation until the DIG_LOOPBK bit is released, at which time the Digital Interface Format of the DAC will operate ac- cording to the format selected in the DAC_DIF(4:3) bits ...
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... Oversampling Modes The CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selec- tion is determined by the FM bits in the Mode Control Register (03h). Single-Speed Mode supports input sample rates from kHz and uses a 128x oversampling ratio. Double-Speed Mode supports input sample rates from 50 to 108 kHz and uses an oversampling ratio of 64x ...
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... Figure 15, and shows the design equations used to Parameter Figure 16 and 17. 0.56*VA (1 Vrms). See shows the input parameters and the associated design equa- Table 8. Analog Input Design Parameters CS4270 µs Frequency Equation ------------------------ - R1 ...
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... Analog Input Figure 15. CS4270 Example Analog Input Network -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 Figure 16. A/D THD+N Performance vs. Input Source Impedance 106 104 102 100 Figure 17. A/D Dynamic Range vs. Input Source Impedance 26 2 k 10 µF (R1 k 220 pF (R2) ...
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... Output Connections The analog output filter present in the CS4270 is a switched-capacitor low pass filter. Its response, com- bined with that of the digital interpolator, is given in circuitry is shown in Figure 3.3 µF AOUTx + CS4270 C = Figure 18. CS4270 Recommended Analog Output Filter 5.6 Mute Control The Mute Control pins become active during power-up initialization, reset, muting, when the MCLK to LRCK ratio is incorrect, and during power-down ...
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... SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4270 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10011 ...
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... INCR ACK ACK Figure 20. Software Mode Timing, I²C Write STOP MAP BYTE CHIP ADDRESS (READ INCR ACK ACK START Figure 21. Software Mode Timing, I²C Read CS4270 DATA DATA +1 DATA + ACK DATA DATA +1 DATA + AD1 AD0 ACK ACK 18. ACK STOP 0 NO ACK ...
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... MAP = Memory Address Pointer, 8 bits, MSB first 30 6.2.3.1) is set to 1, repeat the previous step until all the desired registers 6.2.3.1) is set to 1, keep CS low and continue providing clocks on CCLK DATA LSB MSB 1001111 Figure 22. Software Mode Timing, SPI Mode CS4270 “Switching 18. R/W MSB LSB MSB LSB DS686F1 ...
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... ADC_INV_ ADC_INV_ AUTO_ MUTE_ MUTE_ Reserved MUTE ADC_CHB ADC_CH DACA_ DACA_ DACA_ DACA_ VOL6 VOL5 VOL4 DACB_ DACB_ DACB_ DACB_ VOL6 VOL5 VOL4 CS4270 REV3 REV2 REV1 PDN_DAC MCLK_ MCLK_ FREQ1 FREQ0 Reserved ADC_DIF0 DAC_INV_ DAC_INV_A DE_EMPH MUTE_ MUTE_DAC_ MUTE_DAC_ POL ...
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... The DAC portion of the device enters a low-power state when this bit is set. 8.2.4 Power Down (Bit 0) Function: The device enters a low-power state when this bit is set. The contents of all registers are retained when the device is in power-down ID1 ID0 REV3 Reserved Reserved CS4270 REV2 REV1 REV0 Reserved PDN_DAC PDN DS686F1 ...
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... Reserved Reserved FM1 8.3.1 ADC Functional Mode & Master/Slave Mode (Bits 5:4) Function: In Master Mode, the user must configure the CS4270 Speed Mode with these bits. In Slave Mode, the CS4270 auto-detects the speed mode. FM1 8.3.2 Ratio Select (Bits 3:1) Function: These bits are used to select the clocking ratios ...
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... Right-Justified, 16-bit Data Right-Justified, 24-bit Data Table 11. DAC Digital Interface Formats Table 12 and may be seen in Description I² 24-bit data Table 12. ADC Digital Interface Formats CS4270 2 1 Reserved Reserved ADC_DIF0 “DC Offset Calibration Using the High-Pass “DC Offset Calibration Using the Table 11 and Figures 9– ...
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... DS686F1 ADC_INV_ ADC_INV_ CHB CHA Table 10 on page Mode 0 Changes take effect immediately 1 Zero Cross enabled 0 Soft Ramp enabled 1 Soft Ramp and Zero Cross enabled (default) CS4270 DAC_INV_ DAC_INV_ DE_EMPH CHB CHA 33. 35 ...
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... VOL7 VOL6 VOL5 Function: See Section 8.8 DAC Channel B Volume Control - Address MUTE_ADC_ MUTE_ADC_ CHB CHA Section 5.2.6 “Auto-Mute” on page DACA_ DACA_ VOL4 VOL3 CS4270 2 1 MUTE_DAC_ MUTE_DAC_ MUTE_POL CHB 23 DACA_ DACA_ DACA_ VOL2 VOL1 08h. Figure 0 CHA 0 VOL0 DS686F1 ...
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... The volume changes are implemented as dictated by the DAC_SOFT and DAC_ZC bits in the Transition Control register (see Binary Code 00000000 00000001 00101000 00101001 11111110 11111111 DS686F1 DACB DACB VOL4 VOL3 Section 8.5.2). Volume Setting 0 dB -0.5 dB -20 dB -20.5 dB -127 dB -127.5 dB Table 14. Digital Volume Control CS4270 DACB DACB DACB VOL2 VOL1 VOL0 37 ...
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... Figure 27. DAC Double-Speed Stopband Rejection 38 Figure 24. DAC Single-Speed Transition Band 0.05 0 -0.05 -0. 1 -0.15 -0. 2 -0.25 0 0.05 0.52 0.53 0.54 0.5 5 Figure 26. DAC Single-Speed Passband Ripple Figure 28. DAC Double-Speed Transition Band CS4270 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs) DS686F1 ...
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... Figure 32. DAC Quad-Speed Transition Band 0 - -1. 5 0.65 0.7 0 Figure 34. DAC Quad-Speed Passband Ripple CS4270 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (normalized to Fs) 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Frequency(normalized to Fs) ...
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... Figure 40. ADC Double-Speed Stopband (detail) CS4270 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (norm alized to Fs) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (norm alized to Fs) 0 ...
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... Figure 46. ADC Quad-Speed Passband Ripple CS4270 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Frequency (norm alized to Fs) ...
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... Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 42 CS4270 DS686F1 ...
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... JEDEC #: MO-153 Controlling Dimension is Millimeters. Symbol (Note 4) (Multi-layer PCB) TSSOP JA-M (Single-layer PCB) TSSOP JA-S CS4270 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.20 0.10 0.15 1.00 1.05 0.245 0.30 2,3 7.80 BSC 7 ...
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... SCLK/LRCK ratios to the serial control 30. Section 7. “Register Quick Reference” on page and Section 8.4.2 on page 34. CS4270 Container Order # Rail CS4270-CZZ Tape & Reel CS4270-CZZR - - CDB4270 Figure 1 on page 7. Section 4. “Characteristics and 8. 11. “Power Supply Current” on page 13. “Power Consumption VLC= 13 ...
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... Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS686F1 www.cirrus.com. CS4270 45 ...