DP8344BV National Semiconductor, DP8344BV Datasheet - Page 43

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

2 0 CPU Description
2 2 3 Interrupts
The DP8344B has two external and four internal interrupt
sources The external interrupt sources are the Non-Maska-
ble Interrupt pin NMI and the Bi-directional Interrupt Re-
quest pin BIRQ
External
A non-maskable interrupt is detected by the CPU when a
falling edge is detected at the NMI pin The interrupt is auto-
matically cleared internally when the CPU recognizes the
interrupt
BIRQ can function as both an interrupt into the DP8344B
and as an output which can be used to interrupt other devic-
es BIRQ is configured as an input or output according to
the state of BIC in the Auxiliary Control Register
BIRQ is an input if BIC is a zero and an output when BIC
is a one The reset state of BIC is a zero causing BIRQ to
be an input after the BCP is reset BIRQ in the Condition
Code Register
state of BIRQ regardless of whether BIRQ is configured as
an input or output This bit is updated at the beginning of T1
of each instruction
When BIRQ is configured as an input an interrupt will occur
if the pin is held low BIRQ must be held low until the inter-
rupt is recognized or the interrupt will not be processed Due
to the prioritizing of interrupts as described below BIRQ
may not be recognized by the CPU until higher priority inter-
rupts have been serviced BIRQ will be recognized after
higher priority interrupts have been processed The low
state on BIRQ should be removed after the CPU recognizes
the interrupt or the interrupt will be processed multiple
times
Remote Processor writes a 1 to BIS
CCR
IM3
IM3
0
1
0
1
(a) BIRQ is an Input ( BIC
is a read only bit which mirrors the
(c) BIRQ is an Output ( BIC
IM3
IM3
IM3
IM3
BIS
BIS
(b) BIRQ is an Output ( BIC
e
e
e
e
0
1
0
1
(Continued)
BIS
Active Interrupt to the BCP state of
BIRQ controlled by the Remote
Processor
Masked Interrupt to the BCP state of
BIRQ controlled by the Remote
Processor
State of IM3
State of IM3
TABLE 2-26 BIRQ Control Summary
e
e
e
0) Remote Processor Controls the State of BIRQ
ACR
e
BIRQ
BIRQ
0
1
1) Remote Processor Acknowledges BIRQ
e
Toggles
1) BCP Controls the State of BIRQ
43
IM3
When BIRQ is configured as an output its state is controlled
by IM3 in the Interrupt Control Register
the state of this bit will change BIRQ at the beginning of T1
of the instruction following the write to IM3
Therefore there is a one instruction cycle delay from when
available in BIRQ
ration register
BIRQ is an output writing a one to BIS will change the
state of IME thus changing BIRQ and allowing a remote
processor to acknowledge an interrupt from the BCP Note
if the BCP code operates on IM3 at the same time that the
remote processor acknowledges the interrupt by writing a
one to BIS BIRQ will toggle and then assume the state of
the designer chooses to operate on IM3 while waiting for
the remote processor to acknowledge a BIRQ interrupt the
designer should ensure that the remote processor is locked
out from accessing BIS during the operation on IM3
This can be accomplished by setting LOR in ACR
ing the BCP perform a data memory access to ensure that
any current remote accesses are complete operating an
two T-states after the end of the write to BIS
one to BIS will have no effect on IM3 when BIRQ is an
input Table 2-26 summarizes the relationship between
BIRQ and its associated register bits
BIRQ in CCR is also updated at the beginning of T1
IM3 changes to when the new value of BIRQ is made
IM3 resulting from the BCP code operation Therefore if
IM3
BIS
IM3
and finally clearing LOR
Reflects the state of BIRQ
Reflects the state of BIRQ
Reflects the state of BIRQ
Reflects the state of BIRQ
State of IM3
BIRQ
RIC
BIS in the Remote Interface Configu-
mirrors the state of IM3
BIRQ
BIRQ
Reflects the
state of BIRQ
BIRQ
BIRQ will change state
e
e
0
1
ICR
Note that
Changing
Writing a
When
hav-