DP8344BV National Semiconductor, DP8344BV Datasheet - Page 165

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

6 0 Reference Section
ATR AUXILIARY TRANSCEIVER REGISTER
AT7 –0
Alternate R2 read write
AT7
7
AT6
Auxiliary Transceiver
modes bits 2–0 define the receive station ad-
dress and bits 7–3 control the amount of time
TX-ACT stays asserted after the last fill bit
In 8-bit protocol modes bits 7–0 define the re-
ceive station address
For further information see Section 3 0 Trans-
ceiver
6
ATR 7–3
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
1 1 1 1 1
AT5
5
TX-ACT Hold Time ( s)
AT4
4
(if TCLK
AT3
3
15 5
0 5
1 0
1 5
e
0
(Continued)
8 MHz)
AT2
2
In 5250 protocol
AT1
1
AT0
0
165
CCR CONDITION CODE REGISTER
TO
RR
RW
BIRQ
N
V
C
Z
Main R0 bits 0– 3 5– 7 read write bit 4 read only
TO
7
RR
6
Time Out flag
zero Cleared by writing a 1 to this location or by
stopping timer (by writing a 0 to TST )
Remote Read
REM-RD pulse if RAE is asserted and RIC is
pointing to Data Memory Cleared by writing a 1
to this location
Remote Write
REM-WR pulse if RAE is asserted and RIC is
pointing to Data Memory Cleared by writing a 1
to this location
Bi-directional Interrupt ReQuest
only Reflects the logic level of the Bi-directional
interrupt pin BIRQ Updated at the beginning of
each instruction cycle
Negative
result generated by an arithmetic logical or shift
instruction
oVerflow
condition generated by an arithmetic instruction
Carry
generated by an arithmetic instruction During a
shift rotate operation the state of the last bit shift-
ed out appears in this location
Zero
erated by an arithmetic logical or shift instruction
Further information Section 2 2 1 ALU Section
2 2 3 Interrupts
RW
5
A high level indicates a zero result gen-
A high level indicates a carry or borrow
BIRQ
A high level indicates an overflow
A high level indicates a negative
4
Set high when timer counts to
Set on the trailing edge of a
Set on the trailing edge of a
N
3
2
V
C
1
Read
0
Z