DP8344BV National Semiconductor, DP8344BV Datasheet - Page 164

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

6 0 Reference Section
6 2 1 Bit Index (Continued)
An alphabetical listing of all status control bits in the CPU-addressable special function registers with a brief summary of
function Detailed definitions are provided in Section 6 2 3 Bit Definition Tables
6 2 2 Register Description
A list of all CPU-addressable special function registers in
alphabetical order
The Remote Interface Configuration register RIC which is
addressable only by the remote system is not included See
Section 6 3 Remote Interface Reference for details of the
function of this register
Each register is listed together with its address the type of
access available and a functional description of each bit
Further details on each bit can be found in Section 6 2 3 Bit
Definition Tables
TFE
TFF
TIN
TLD
TM7–0
TM15–8
TMC
TO
TRES
TST
V
Z
Bit
Transmit FIFO Empty
Transmit FIFO Full
Transmitter INvert
Timer LoaD
TiMer
TiMer
TiMer Clock select
Time Out flag
Transceiver RESet
Timer StarT
oVerflow
Zero
(Continued)
Name
164
ACR AUXILIARY CONTROL REGISTER
rsv
TST
TLD
TMC
BIC
COD
LOR
GIE
4TR
Main R3 read write
TST
7
NCF
TSR
TMR
ACR
TRL
TRH
ACR
CCR
TMR
ACR
CCR
CCR
Location
state is undefined at all times
TLD
6
Timer StarT
and will count down from it’s current value
When low timer is disabled Timer is stopped by
writing a 0 to TST
Timer LoaD
pulse Cleared when load complete
TiMer Clock select
quency Should not be written when TST is
high Can be written at same time as TST and
Bi-directional Interrupt Control
rection of BIRQ
Clock Out Disable
put is at TRI-STATE
Lock Out Remote
tem is prevented from accessing the BCP
Global Interrupt Enable
all maskable interrupts When high works with
4 T-state Read
ing is changed to allow more time between the
TRI-STATE of the AD lines by the BCP and the
falling of the READ strobe All data memory reads
take four T-states when this bit is set See Sec-
tion 2 2 2 for more information
7
7
3
6
5
7
7
7
2
0
7–0
7–0
TLD
IM4– 0 to enable maskable interrupts
TMC
5
TMC
0
1
BIC
0
1
BIC
4
(CPU-CLK) 16
(CPU-CLK) 2
Timer Clock
When high generates timer load
When high the timer is enabled
Transmitter Status
Transmitter Status
Transmitter Control
Timer
Timer
Timer
Timer
Timer
Transceiver Control
Timer
Arithmetic Flag
Arithmetic Flag
When high READ strobe tim-
Input
Output
rsv
BIRQ
3
When high CLK-OUT out-
When high a remote sys-
Function
Selects timer clock fre-
COD
When low disables
2
LOR
1
Controls di-
GIE
0