MPC885CVR133 Freescale Semiconductor, MPC885CVR133 Datasheet - Page 42
MPC885CVR133
Manufacturer Part Number
MPC885CVR133
Description
IC MPU POWERQUICC 133MHZ 357PBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC880VR80.pdf
(87 pages)
Specifications of MPC885CVR133
Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
133MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
133 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
Data Ram Size
8 KB
I/o Voltage
5 V
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
0 C
Program Memory Size
8 KB
Program Memory Type
EPROM/Flash
For Use With
CWH-PPC-885XN-VX - BOARD EVAL QUICCSTART MPC885CWH-PPC-885XN-VE - BOARD EVAL QUICCSTART MPC885
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC885CVR133
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MPC885CVR133
Manufacturer:
MOTOROLA
Quantity:
745
Company:
Part Number:
MPC885CVR133
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Bus Signal Timing
Table 14
42
Num
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R82
CLKOUT to HRESET high impedance
(MAX = 0.00 × B1 + 20.00)
CLKOUT to SRESET high impedance
(MAX = 0.00 × B1 + 20.00)
RSTCONF pulse width
(MIN = 17.00 × B1)
Configuration data to HRESET rising
edge setup time
(MIN = 15.00 × B1 + 50.00)
Configuration data to RSTCONF rising
edge setup time
(MIN = 0.00 × B1 + 350.00)
Configuration data hold time after
RSTCONF negation
(MIN = 0.00 × B1 + 0.00)
Configuration data hold time after
HRESET negation
(MIN = 0.00 × B1 + 0.00)
HRESET and RSTCONF asserted to
data out drive
(MAX = 0.00 × B1 + 25.00)
RSTCONF negated to data out high
impedance (MAX = 0.00 × B1 + 25.00)
CLKOUT of last rising edge before chip
three-states HRESET to data out high
impedance (MAX = 0.00 × B1 + 25.00)
DSDI, DSCK setup (MIN = 3.00 × B1)
DSDI, DSCK hold time
(MIN = 0.00 × B1 + 0.00)
SRESET negated to CLKOUT rising
edge for DSDI and DSCK sample
(MIN = 8.00 × B1)
shows the reset timing for the MPC885/MPC880.
Characteristic
—
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Table 14. Reset Timing
515.20
504.50
350.00
242.40
90.90
0.00
0.00
0.00
Min
—
—
—
—
—
—
33 MHz
20.00
20.00
25.00
25.00
25.00
Max
—
—
—
—
—
—
—
—
—
425.00
425.00
350.00
200.00
75.00
0.00
0.00
0.00
Min
—
—
—
—
—
—
40 MHz
20.00
20.00
25.00
25.00
25.00
Max
—
—
—
—
—
—
—
—
—
257.60
277.30
350.00
121.20
45.50
0.00
0.00
0.00
Min
—
—
—
—
—
—
66 MHz
20.00
20.00
25.00
25.00
25.00
Max
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
212.50
237.50
350.00
100.00
37.50
0.00
0.00
0.00
Min
—
—
—
—
—
—
80 MHz
20.00
20.00
25.00
25.00
25.00
Max
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns