MPC885CVR133 Freescale Semiconductor, MPC885CVR133 Datasheet - Page 16

• Manufacturer Part Number: MPC885CVR133
• Description: IC MPU POWERQUICC 133MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC885CVR133

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 133 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• I/o Voltage: 5 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: 0 C
• Program Memory Size: 8 KB
• Program Memory Type: EPROM/Flash
• For Use With: CWH-PPC-885XN-VX - BOARD EVAL QUICCSTART MPC885CWH-PPC-885XN-VE - BOARD EVAL QUICCSTART MPC885
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Layout Practices
9
Each V
supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The V
using at least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package.
Each board designed should be characterized and additional appropriate decoupling capacitors should be
used if required. The capacitor leads and associated printed-circuit traces connecting to chip V
GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board
employing two inner layers as V
All output pins on the MPC885/MPC880 have fast rise and fall times. Printed-circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections caused by
these fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V
inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For
more information, please refer to the MPC885 PowerQUICC™ Family Reference Manual, Section 14.4.3,
“Clock Synthesizer Power (V
10 Bus Signal Timing
The maximum bus speed supported by the MPC885/MPC880 is 80 MHz. Higher-speed parts must be
operated in half-speed bus mode (for example, an MPC885/MPC880 used at 133 MHz must be configured
for a 66 MHz bus).
Table 8
16
Layout Practices
DD
shows the frequency ranges for standard part frequencies in 2:1 bus mode.
pin on the MPC885/MPC880 should be provided with a low-impedance path to the board’s
Table 7
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
shows the frequency ranges for standard part frequencies in 1:1 bus mode, and
DDSYN
Figure 5. Example Voltage Sequencing Circuit
DD
DD
and GND planes should be used.
and GND circuits. Pull up all unused inputs or signals that will be
, V
V
DDH
SSSYN
, V
MUR420
SSSYN1
1N5820
).”
DD
power supply should be bypassed to ground
V
DDL
Freescale Semiconductor
DD
and