CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet - Page 34

• Manufacturer Part Number: CY7C64013-SC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-SC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1327

Bits[2..0] : Control Action
Table 17-1. Control Bit Definition for Upstream Port
Bit 3 : Bus Activity
Bits 4 and 5 : D– Upstream and D+ Upstream
Bit 6 : Endpoint Mode
Bit 7 : Endpoint Size
18.0
USB Device Address A includes up to five endpoints: EPA0, EPA1, EPA2, EPA3, and EPA4. Endpoint (EPA0) allows the USB
host to recognize, set-up, and control the device. In particular, EPA0 is used to receive and transmit control (including set-up)
packets.
18.1
The USB Controller provides one USB Device Address with five endpoints. The USB Device Address Register contents are
cleared during a reset, setting the USB device address to zero and marking this address as disabled. Figure 18-1 shows the
format of the USB Address Registers.
USB Device Address
Document #: 38-08001 Rev. *A
USB Status and Control
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Control Bits
000
001
010
100
101
011
110
Set to control action as per Table 17-1.The three control bits allow the upstream port to be driven manually by firmware. For normal
USB operation, all of these bits must be cleared. Table 17-1 shows how the control bits affect the upstream port.
111
This is a “sticky” bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware should check and clear
this bit periodically to detect any loss of bus activity. Writing a ‘0’ to the Bus Activity bit clears it, while writing a ‘1’ preserves the
current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.
These bits give the state of each upstream port pin individually: 1 = HIGH, 0 = LOW.
This bit used to configure the number of USB endpoints. See Section 18.2 for a detailed description.
This bit used to configure the number of USB endpoints. See Section 18.2 for a detailed description.
USB Device Address
USB Serial Interface Engine Operation
Device Address
Endpoint Size
Not Forcing (SIE Controls Driver)
Force D+[0] HIGH, D–[0] LOW
Force D+[0] LOW, D–[0] HIGH
Force SE0; D+[0] LOW, D–[0] LOW
Force D+[0] LOW, D–[0] LOW
Force D+[0] HiZ, D–[0] LOW
Force D+[0] LOW, D–[0] HiZ
Force D+[0] HiZ, D–[0] HiZ
Enable
R/W
R/W
7
0
7
0
Device Address
Endpoint Mode
Control Action
R/W
Bit 6
R/W
6
0
6
0
Figure 17-1. USB Status and Control Register
Figure 18-1. USB Device Address Registers
Device Address
D+ Upstream
Bit 5
R/W
R
5
0
5
0
Device Address
D– Upstream
Bit 4
R/W
R
4
0
4
0
Device Address
Bus Activity
R/W
Bit 3
R/W
3
0
3
0
Device Address
Control Action
Bit 2
Bit 2
R/W
R/W
2
0
2
0
Device Address
Control Action
Bit 1
R/W
Bit 1
R/W
1
0
1
0
CY7C64013
CY7C64113
ADDRESSES
ADDRESS 0x1F
Page 34 of 51
Device Address
Control Action
Bit 0
R/W
Bit 0
R/W
0
0
0
0
0x10