CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet - Page 23

• Manufacturer Part Number: CY7C64013-SC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-SC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1327

Bit [4..0]: Isink [x] (x= 0..4)
Bit [7..5]: Reserved
10.2
A DAC port interrupt can be enabled/disabled for each pin individually. The DAC Port Interrupt Enable register provides this
feature with an interrupt enable bit for each DAC I/O pin.All of the DAC Port Interrupt Enable register bits are cleared to ‘0’ during
a reset. All DAC pins share a common interrupt, as explained in Section 16.6.
DAC Port Interrupt
Bit [7..0]: Enable bit x (x= 0..2, 7)
As an additional benefit, the interrupt polarity for each DAC pin is programmable with the DAC Port Interrupt Polarity register.
Writing a ‘0’ to a bit selects negative polarity (falling edge) that causes an interrupt (if enabled) if a falling edge transition occurs
on the corresponding input pin. Writing a ‘1’ to a bit in this register selects positive polarity (rising edge) that causes an interrupt
(if enabled) if a rising edge transition occurs on the corresponding input pin. All of the DAC Port Interrupt Polarity register bits are
cleared during a reset.
DAC Port Interrupt Polarity
Bit [7..0]: Enable bit x (x= 0..2, 7)
11.0
The 12-bit timer provides two interrupts (128-µs and 1.024-ms) and allows the firmware to directly time events that are up to 4
ms in duration. The lower 8 bits of the timer can be read directly by the firmware. Reading the lower 8 bits latches the upper 4
bits into a temporary register. When the firmware reads the upper 4 bits of the timer, it is accessing the count stored in the
temporary register. The effect of this logic is to ensure a stable 12-bit timer value can be read, even when the two reads are
separated in time.
Bit [7:0]: Timer lower 8 bits
Document #: 38-08001 Rev. *A
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Timer LSB
Bit #
Bit Name
Read/Write
Reset
Writing all ‘0’s to the Isink register causes 1/5 of the max current to flow through the DAC I/O pin. Writing all ‘1’s to the
Isink register provides the maximum current flow through the pin. The other 14 states of the DAC sink current are evenly
spaced between these two values.
DAC Port Interrupts
1= Selects positive polarity (rising edge) that causes an interrupt (if enabled);
0= Selects negative polarity (falling edge) that causes an interrupt (if enabled)
1= Enables interrupts from the corresponding bit position; 0= Disables interrupts from the corresponding bit position
12-Bit Free-Running Timer
Enable Bit 7
Enable Bit 7
Timer Bit 7
W
W
7
0
7
0
R
7
0
Timer Bit 6
Reserved
Reserved
W
W
6
0
6
0
R
6
0
Figure 10-5. DAC Port Interrupt Polarity
Figure 10-4. DAC Port Interrupt Enable
Timer Bit 5
Reserved
Reserved
Figure 11-1. Timer LSB Register
W
W
R
5
0
5
0
5
0
Timer Bit 4
Reserved
Reserved
W
W
R
4
0
4
0
4
0
Timer Bit 3
Reserved
Reserved
W
W
R
3
0
3
0
3
0
Enable Bit 2
Enable Bit 2
Timer Bit 2
W
W
R
2
0
2
0
2
0
Enable Bit 1
Enable Bit 1
Timer Bit 1
W
W
R
1
0
1
0
1
0
CY7C64013
CY7C64113
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ADDRESS 0x32
ADDRESS 0x31
ADDRESS 0x24
Enable Bit 0
Enable Bit 0
Timer Bit 0
R
W
W
0
0
0
0
0
0