CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet - Page 33

• Manufacturer Part Number: CY7C64013-SC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-SC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1327

The Continue/Busy bit is cleared by hardware prior to interrupt conditions 1 to 4. Once the Data Register has been read or written,
firmware should configure the other control bits and set the Continue/Busy bit for subsequent transactions. Following an interrupt
from master mode, firmware should perform only one write to the Status and Control Register that sets the Continue/Busy bit,
without checking the value of the Continue/Busy bit. The Busy bit may otherwise be active and I
changed by the hardware during the transaction, until the I
17.0
The USB hardware consists of the logic for a full-speed USB Port. The full-speed serial interface engine (SIE) interfaces the
microcontroller to the USB bus. An external series resistor (R
the corresponding pins as possible, to meet the USB driver requirements of the USB specifications.
17.1
The SIE allows the CY7C64x13 microcontroller to communicate with the USB host. The SIE simplifies the interface between the
microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the microcon-
troller:
Firmware is required to handle the following USB interface tasks:
17.2
The USB device is enumerated under firmware control. The following is a brief summary of the typical enumeration process of
the CY7C64x13 by the USB host. For a detailed description of the enumeration process, refer to the USB specification.
In this description, ‘Firmware’ refers to embedded firmware in the CY7C64x13 controller.
10.Once the device receives a Set Configuration request, its functions may now be used.
17.3
USB status and control is regulated by the USB Status and Control Register, as shown in Figure 17-1. All bits in the register are
cleared during reset.
Document #: 38-08001 Rev. *A
5. In master receive mode, after the master receives a byte of data: Firmware should read the data and set the ACK and Continue/Busy bits
6. When the master loses arbitration: This condition clears the MSTR MODE bit and sets the ARB Lost/Restart bit immediately and then waits
1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor.
2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables.
3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB bus, via the
4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB address to
5. Firmware stores the new address in its USB Device Address Register after the no-data control sequence completes.
6. The host sends a request for the Device descriptor using the new USB address.
7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.
8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus.
9. The host generates control reads from the device to request the Configuration and Report descriptors.
• Bit stuffing/unstuffing
• Checksum generation/checking
• ACK/NAK/STALL
• Token type identification
• Address checking
• Coordinate enumeration by responding to SETUP packets
• Fill and empty the FIFOs
• Suspend/Resume coordination
• Verify and select DATA toggle values
appropriately for the next byte. Clearing the MSTR MODE bit at the same time causes the master state machine to issue a stop signal to
the I
for a stop signal on the I
on-chip FIFOs.
the device.
2
C-compatible bus and leave the I
USB Serial Interface Engine (SIE)
USB Enumeration
USB Upstream Port Status and Control
USB Overview
2
C-compatible bus to generate the interrupt.
2
C-compatible hardware in the idle state.
2
C interrupt occurs.
ext
) must be placed in series with the D+ and D– lines, as close to
2
C register contents may be
CY7C64013
CY7C64113
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