CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet - Page 21

• Manufacturer Part Number: CY7C64013-SC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-SC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1327

Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1. The available GPIO drive strength are:
9.2
Each GPIO pin can be individually enabled or disabled as an interrupt source. The Port 0–3 Interrupt Enable registers provide
this feature with an interrupt enable bit for each GPIO pin. When HAPI mode (discussed in Section 14.0) is enabled the GPIO
interrupts are blocked, including ports not used by HAPI, so GPIO pins cannot be used as interrupt sources.
During a reset, GPIO interrupts are disabled by clearing all of the GPIO interrupt enable ports. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in
Section 16.7
Port 0 Interrupt Enable
Port 2 Interrupt Enable
Port 3 Interrupt Enable
10.0
The CY7C64113 features a programmable current sink 4 bit port which is also known as a DAC port. Each of these port I/O pins
have a programmable current sink. Writing a ‘1’ to a DAC I/O pin disables the output current sink (Isink DAC) and drives the I/O
pin HIGH through an integrated 14-kΩ resistor. When a ‘0’ is written to a DAC I/O pin, the Isink DAC is enabled and the pull-up
resistor is disabled. This causes the I
DAC port pin.
Document #: 38-08001 Rev. *A
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
• Output LOW Mode: The pin’s Data Register is set to ‘0’
• Output HIGH Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘10’
• Resistive Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘11’
• Hi-Z Mode: The pin’s Data Register is set to1 and Port Configuration Bits[1:0] is set either ‘00’ or ‘01’
Writing ‘0’ to the pin’s Data Register puts the pin in output LOW mode, regardless of the contents of the Port Configuration Bits[1:0]. In
this mode, Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is driven LOW through Q3.
In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is pulled up through Q2. The GPIO pin is capable of sourcing... of current.
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with an internal 14kΩ resistor. In resistive mode, the pin may serve as an input.
Reading the pin’s Data Register returns a logic HIGH if the pin is not driven LOW by an external source.
Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven internally. In this mode, the pin may serve as an input. Reading the Port Data
Register returns the actual logic value on the port pins.
GPIO Interrupt Enable Ports
DAC Port
P0.7 Intr Enable P0.6 Intr Enable P0.5 Intr Enable P0.4 Intr Enable P0.3 Intr Enable P0.2 Intr Enable P0.1 Intr Enable P0.0 Intr Enable
P1.7 Intr Enable P1.6 Intr Enable P1.5 Intr Enable P1.4 Intr Enable
P2.7 Intr Enable P2.6 Intr Enable P2.5 Intr Enable P2.4 Intr Enable P2.3 Intr Enable P2.2 Intr Enable P2.1 Intr Enable P2.0 Intr Enable
Reserved
(Set to 0)
W
W
W
W
7
0
7
0
7
0
7
0
P3.6 Intr Enable P3.5 Intr Enable P3.4 Intr Enable P3.3 Intr Enable P3.2 Intr Enable P3.1 Intr Enable P3.0 Intr Enable
W
W
W
W
6
0
6
0
6
0
6
0
sink
DAC to sink current to drive the output LOW. Figure 10-1 shows a block diagram of the
Figure 9-10. Port 3 Interrupt Enable
Figure 9-7. Port 0 Interrupt Enable
Figure 9-8. Port 1 Interrupt Enable
Figure 9-9. Port 2 Interrupt Enable
W
W
W
W
5
0
5
0
5
0
5
0
W
W
W
W
4
0
4
0
4
0
4
0
P1.3 Intr Enabl
W
W
W
W
3
0
3
0
3
0
3
0
P1.2 Intr Enable P1.1 Intr Enable P1.0 Intr Enable
W
W
W
W
2
0
2
0
2
0
2
0
W
W
W
W
1
0
1
0
1
0
1
0
CY7C64013
CY7C64113
Page 21 of 51
ADDRESS 0x04
ADDRESS 0x06
ADDRESS 0x07
W
W
W
W
0
0
0
0
0
0
0
0