CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet - Page 25

• Manufacturer Part Number: CY7C64013-SC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-SC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1327

Table 12-1. HAPI Port Configuration
Table 12-2. I
13.0
The I
master modes of operation. The I
interrupts as needed to allow firmware to take appropriate action during transactions. While waiting for firmware response, the
hardware keeps the I
The I
stop bit is detected by the slave when in receive mode, or when arbitration is lost. Details of the interrupt responses are given in
Section 16.8.
The I
(Figure 13-2). The Data Register is implemented as separate read and write registers. Generally, the I
Register should only be monitored after the I
read misleading bit status if a transaction is underway.
The I
1 or GPIO port 2. Refer to Section 12.0 for the bit definitions and functionality of the HAPI/I
used to set the locations of the configurable I
0 of the I
regardless of the settings of the GPIO Configuration Register.The electrical characteristics of the I
same as that of GPIO ports 1 and 2. Note that the I
All control of the I
I
Bits [7..0] : I
I
The I
Document #: 38-08001 Rev. *A
2
2
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
C Data
C Status and Control
Port Width (Bits[1:0])
2
2
2
2
2
C-compatible block provides a versatile two-wire communication with external devices, supporting master, slave, and multi-
C-compatible interface consists of two registers, an I
Contains the 8 bit data on the I
C-compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte, when a
C SCL clock is connected to bit 0 of GPIO port 1 or GPIO port 2, and the I
C Status and Control register bits are defined in Table 14-1, with a more detailed description following.
2
I
C Status & Control Register, the two LSB bits ([1:0]) of the corresponding GPIO port are placed in Open Drain mode,
I
2
2
10
01
00
11
C Position (Bit[7])
C-compatible Controller
2
2
C Port Configuration
C Data
MSTR Mode
I
2
2
C clock and data lines is performed by the I
C Data 7
R/W
R/W
X
0
1
X
7
7
0
2
C-compatible bus idle if necessary.
24 Bits: P3[7:0], P1[7:0], P0[7:0]
Continue/Busy
16 Bits: P1[7:0], P0[7:0]
I
2
C Data 6
No HAPI Interface
R/W
R/W
HAPI Port Width
2
2
X
6
C Bus
6
0
C-compatible block functions by handling the low-level signaling in hardware, and issuing
8 Bits: P0[7:0]
Figure 13-2. I
2
2
C interrupt, as all bits are valid at that time. Polling this register at other times could
Xmit Mode
I
C-compatible pins. Once the I
2
C Data 5
R/W
Figure 13-1. I
R/W
5
X
5
0
OL
Port Width (Bit[1])
(max) is 2 mA @ V
2
C Status and Control Register
2
C Data Register (Figure 13-1) and an I
I
2
1
0
0
C Data 4
2
ACK
2
R/W
R/W
C Data Register
C-compatible block.
X
4
4
0
OL
I
2
C Data 3
2
Addr
R/W
R/W
= 2.0 V for ports 1 and 2.
C-compatible functionality is enabled by setting bit
X
3
3
0
2
C SDA data is connected to bit 1 of GPIO port
Lost/Restart
I
2
C Data 2
I
I
I
ARB
R/W
R/W
2
2
2
X
C on P2[1:0], 0:SCL, 1:SDA
C on P1[1:0], 0:SCL, 1:SDA
C on P2[1:0], 0:SCL, 1:SDA
2
2
0
2
C Configuration Register, which is
2
2
C Status and Control Register
I
C-compatible interface is the
2
C Position
Received Stop
I
2
C Data 1
R/W
R/W
2
X
1
1
0
C Status and Control
CY7C64013
CY7C64113
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ADDRESS 0x29
I
I
2
2
C Enable
C Data 0
R/W
R/W
0
X
0
0