AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 71

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AN2131QC

Manufacturer Part Number
AN2131QC
Description
IC MCU 8051 8K RAM 24MHZ 80BQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB®r
Datasheet

Specifications of AN2131QC

Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
AN213x
Ram Size
8K x 8
Interface
I²C, USB
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1307

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ACK bit at the same time it sets DONE=1. The ACK bit should be ignored for read trans-
fers on the bus.
4.7.3 BERR
This bit indicates an I
which results when an outside device drives the bus LO when it shouldn’t, or when
another bus master wins arbitration, taking control of the bus. BERR is cleared when the
8051 reads or writes the I2DAT register.
4.7.4 ID1, ID0
These bits are set by the boot loader (Section 4.10, "I
an 8-bit address or 16-bit address EEPROM at slave address 000 or 001 was detected at
power-on. They are normally used only for debug purposes. Table 4-3 shows the encod-
ing for these bits.
To send a multiple byte data record over the I
* If the I
Page 4-10
4.8
rupt driven, and handled by an interrupt service routine. See Section 9.12, "I
rupt” for more details regarding the I
1. Set the START bit.
2. Write the peripheral address and direction=0 (for write) to I2DAT.
3. Wait for DONE=1*. If BERR=1 or ACK=0, go to step 7.
4. Load I2DAT with a data byte.
5. Wait for DONE=1*. If BERR=1 or ACK=0 go to step 7.
6. Repeat steps 4 and 5 for each byte until all bytes have been transferred.
7. Set STOP=1.
Sending I
2
C interrupt (8051 INT3) is enabled, each “Wait for DONE=1” step can be inter-
2
C Data
2
C bus error. BERR=1 indicates that there was bus contention,
Chapter 4. EZ-USB CPU
2
C interrupt.
2
C bus, follow these steps:
2
C Boot Loader") to indicate whether
EZ-USB TRM v1.9
2
C Inter-

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