AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 226
AN2131QC
Manufacturer Part Number
AN2131QC
Description
IC MCU 8051 8K RAM 24MHZ 80BQFP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB®r
Datasheet
1.AN2131SC.pdf
(334 pages)
Specifications of AN2131QC
Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
AN213x
Ram Size
8K x 8
Interface
I²C, USB
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1307
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Bit 0:
The 8051 sets this bit to “1” to stall an endpoint, and to “0” to clear a stall.
When the stall bit is “1,” the EZ-USB core returns a STALL Handshake for all requests to
the endpoint. This notifies the host that something unexpected has happened.
The 8051 sets an endpoint’s stall bit under two circumstances:
The 8051 clears an endpoint’s stall bit under two circumstances:
All stall bits are automatically cleared when the EZ-USB chip ReNumerates
the DISCON bit HI.
EZ-USB TRM v1.9
1. The host sends a “Set_Feature—Endpoint Stall” request to the specific endpoint.
2. The 8051 encounters any show stopper error on the endpoint, and sets the stall bit
1. The host sends a “Clear_Feature--Endpoint Stall” request to the specific endpoint.
2. The 8051 receives some other indication from the host that the stall should be
to tell the host to halt traffic to the endpoint.
cleared (this is referred to as “host intervention” in the USB Specification). This
indication could be a USB bus reset.
INnSTL
IN Endpoint (1-7) Stall
Chapter 12. EZ-USB Registers
by pulsing
Page 12-33
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