AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 125

• Manufacturer Part Number: AN2131QC
• Description: IC MCU 8051 8K RAM 24MHZ 80BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2131QC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1307

USB registers starting at SETUPDAT. The EZ-USB core takes care of any re-tries if it
finds any errors in the SETUP data. These two interrupt request bits are set by the EZ-
USB core, and must be cleared by firmware.
An 8051 program responds to the SUDAV interrupt request by either directly inspecting
the eight bytes at SETUPDAT or by transferring them to a local buffer for further process-
ing. Servicing the SETUP data should be a high 8051 priority, since the USB Specifica-
tion stipulates that CONTROL transfers must always be accepted and never NAKd. It is
therefore possible that a CONTROL transfer could arrive while the 8051 is still servicing
a previous one. In this case the previous CONTROL transfer service should be aborted
and the new one serviced. The SUTOK interrupt gives advance warning that a new CON-
TROL transfer is about to over-write the eight SETUPDAT bytes.
If the 8051 stalls endpoint zero (by setting the EP0STALL and HSNAK bits to 1), the EZ-
USB core automatically clears this stall bit when the next SETUP token arrives.
Like all EZ-USB interrupt requests, the SUTOKIR and SUDAVIR bits can be directly
tested and reset by the CPU (they are reset by writing a “1”). Thus, if the corresponding
interrupt enable bits are zero, the interrupt request conditions can still be directly polled.
Figure 7-3 shows the EZ-USB registers that deal with CONTROL transactions over EP0.
These registers augment those associated with normal bulk transfers over endpoint zero,
which are described in Chapter 6, "EZ-USB Bulk Transfers."
Page 7-4
USBIRQ
USBIEN
Interrupt Control
T=Setup Token SUTOKIE
D=Setup Data SUDAVIE
D=Setup Data
T=Setup Token SUTOKIR
Initialization
Registers Associated with Endpoint Zero
Figure 7-3. Registers Associated with EP0 Control Transfers
Interrupt Request:
Global Enable:
For handling SETUP transactions
SUDAVIR
T
T
Chapter 7. EZ-USB CPU
D
D
SETUPDAT
SUDPTRH
SUDPTRL
Data transfer
15
7
14
6
SETUP Data
13
5
8 Bytes of
12
4
11
3
10
2
EZ-USB TRM v1.9
9
1
8
0