AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 229

• Manufacturer Part Number: AN2131QC
• Description: IC MCU 8051 8K RAM 24MHZ 80BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2131QC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1307

The 8051 clears an endpoint’s stall bit under two circumstances:
All stall bits are automatically cleared when the EZ-USB chip ReNumerates .
* See Table 12-5 for individual control/status register addresses.
The 8051 reads this register to determine the number of bytes sent to an OUT endpoint.
Legal sizes are 0 - 64 bytes.
Each EZ-USB bulk OUT endpoint has a byte count register, which serves two purposes.
The 8051 reads the byte count register to determine how many bytes were received during
the last OUT transfer from the host. The 8051 writes the byte count register (with any
value) to tell the EZ-USB core that it has finished reading bytes from the buffer, making
the buffer available to accept the next OUT transfer. Writing the byte count register sets
the endpoint’s BSY bit to “1.”
When the register-pairing feature is used, OUT2BC is used for the EP2/EP3 pair,
OUT4BC is used for the EP4/EP5 pair, and OUT6BC is used for the EP6/EP7 pair. The
odd-numbered byte count registers should not be used. When the 8051 writes a byte to the
even numbered byte count register, the EZ-USB core switches buffers. If the other buffer
already contains data to be read by the 8051, the OUTnBSY bit remains at “0.”
All OUT tokens are NAKd until the 8051 is released from RESET, whereupon the ACK/
NAK behavior is based on pairing.
Page 12-36
OUTnBC
2. The 8051 encounters any show stopper error on the endpoint, and sets the stall bit
1. The host sends a “Clear_Feature—Endpoint Stall” request to the specific endpoint.
2. The 8051 receives some other indication from the host that the stall should be
b7
R
0
-
to tell the host to halt traffic to the endpoint.
cleared (this is referred to as “host intervention” in the USB Specification).
D6
b6
R
0
D5
b5
R
0
Endpoint (1-7) OUT Byte Count
Figure 12-29. OUT Byte Count Registers
Chapter 12. EZ-USB Registers
D4
b4
R
0
D3
b3
R
0
D2
b2
R
0
D1
b1
R
0
7FC7-7FD3*
EZ-USB TRM v1.9
R/W
D0
b0
0