EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 421

• Manufacturer Part Number: EP4CE40F29C8N
• Description: IC CYCLONE IV FPGA 40K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE40F29C8N

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1134000
• Number Of I /o: 532
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–15. Option 3 for Receiver Core Clocking (Channel Reconfiguration Mode)
PLL Reconfiguration Mode
© December 2010 Altera Corporation
FPGA Fabric
rx_clkout[1]
rx_clkout[0]
f
Low-speed parallel clock
High-speed serial clock generated by the MPLL
Figure 3–15
receiver channels of a transceiver block.
Cyclone IV GX device support the PLL reconfiguration support through the
ALTPLL_RECONFIG MegaWizard. You can use this mode to reconfigure the
multipurpose PLL or general purpose PLL used to clock the transceiver channel
without affecting the remaining blocks of the channel. When you reconfigure the
multipurpose PLL or general purpose PLL
data rate, all the transceiver channels listening to this multipurpose PLL or general
purpose PLL
affected. When you reconfigure the multipurpose PLL or general purpose PLL to support
a different data rate, you must ensure that the functional mode of the transceiver channel
supports the reconfigured data rate.
T
Reconfiguration option in the ALTGX MegaWizard under Reconfiguration Setting
tab. For multipurpose PLL or general purpose PLL reconfiguration, .mif files are
required to dynamically reconfigure the PLL setting in order to change the output
frequency of the transceiver PLL to support different data rates.
The .mif files carries the reconfiguration information that will be used to reconfigure
the multipurpose PLL or general purpose PLL dynamically. The .mif contents is
generated automatically when you select the Enable PLL Reconfiguration option in
the Reconfiguration Setting in ALTGX instances. The .mif files will be generated
based on the data rate and input reference clock setting in the ALTGX MegaWizard.
You must use the external ROM and feed its content to the ALTPLL_RECONFIG
megafunction to reconfigure the multipurpose PLL setting.
For more information about instantiating the ALTPLL_Reconfig, refer to the
Implementing Dynamic Reconfiguration in Cyclone IV GX
he PLL reconfiguration mode can be enabled by selecting the Enable PLL
shows the respective rx_clkout of each channel clocking the respective
also get reconfigured to the new data rate. Channel settings are not
Transceiver Block
TX0
RX0
TX1
RX1
of a transceiver block to run at a different
Devices.
Cyclone IV Device Handbook, Volume 2
MPLL
AN 609:
3–31