EP4CE40F29C8N Altera, EP4CE40F29C8N Datasheet - Page 314
EP4CE40F29C8N
Manufacturer Part Number
EP4CE40F29C8N
Description
IC CYCLONE IV FPGA 40K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE40F29C8N
Number Of Logic Elements/cells
39600
Number Of Labs/clbs
2475
Total Ram Bits
1134000
Number Of I /o
532
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA43
Quantity:
1 602
Part Number:
EP4CE40F29C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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1–34
Cyclone IV Device Handbook, Volume 2
1
When implementing ×2 bonded channel configuration in a transceiver block,
remaining channels 2 and 3 are available to implement other non-bonded channel
configuration.
Figure 1–36
low-speed clock distributions for transceivers in F324 and smaller packages, and in
F484 and larger packages in bonded (×2 and ×4) channel configuration.
Figure 1–36. Clock Distribution in Bonded (×2 and ×4) Channel Configuration for Transceivers in
F324 and Smaller Packages.
Notes to
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
(2) High-speed clock.
(3) Low-speed clock.
(4) Bonded common low-speed clock path.
Figure 1–36
Transceiver
GXBL0
Block
and
2 Bonded Channel Configuration
:
Ch3
Ch2
Ch1
Ch0
Figure 1–37
(1)
(1)
MPLL_2
MPLL_1
TX PMA
TX PMA
TX PMA
TX PMA
(4)
show the independent high-speed clock and bonded
(3)
(2)
Transceiver
GXBL0
Block
Chapter 1: Cyclone IV Transceivers Architecture
4 Bonded Channel Configuration
Ch3
Ch2
Ch1
Ch0
(1)
(1)
MPLL_2
MPLL_1
TX PMA
TX PMA
TX PMA
TX PMA
© December 2010 Altera Corporation
Transceiver Clocking Architecture
(4)
(2)
(3)
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