EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 7

IC STRATIX II GX 60K 1152-FBGA

EP2SGX60EF1152I4

Manufacturer Part Number
EP2SGX60EF1152I4
Description
IC STRATIX II GX 60K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX60EF1152I4

Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
60440
# I/os (max)
534
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2186

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX60EF1152I4
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX60EF1152I4
Manufacturer:
ALTERA
0
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
Quantity:
534
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
0
Part Number:
EP2SGX60EF1152I4N
Manufacturer:
ALTERA
Quantity:
300
Part Number:
EP2SGX60EF1152I4N
0
Referenced
Document
Document
Revision History
Altera Corporation
October 2007
Date and Document
October 2007, v1.6
August 2007, v1.5
February 2007, v1.4
June 2006, v1.3
April 2006, v1.2
February 2006, v1.1
October 2005
v1.0
Table 1–4. Document Revision History
Version
Updated
Minor text edits.
Added “Referenced Documents” section.
Minor text edits.
Added the “Document Revision History”
section to this chapter.
Added chapter to the Stratix II GX Device
Handbook.
Changed 622 Mbps to 600 Mbps on
page 1-2 and Table 1–1.
Deleted “DC coupling” from the
Transceiver Block Features list.
Changed 4 to 6 in the PLLs row
(columns 3 and 4) of Table 1–1.
Updated Table 1–2.
Updated Table 1–1.
Updated Table 1–2.
Updated Table 1–1.
This chapter references the following document:
Table 1–4
Pitch (mm)
Area (mm
Length width (mm × mm)
“Features”
Table 1–3. Stratix II GX FineLine BGA Package Sizes
Stratix II GX Architecture
Device Handbook
Changes Made
Dimension
2
shows the revision history for this chapter.
)
section.
780 Pins
chapter in volume 1 of the Stratix II GX
29 × 29
1.00
841
Added support information for the
Stratix II GX device.
Updated numbers for receiver channels and
user I/O pin counts in Table 1–2.
Stratix II GX Device Handbook, Volume 1
Summary of Changes
1,152 Pins
35 × 35
1,225
1.00
1,508 Pins
Introduction
40 × 40
1,600
1.00
1–5

Related parts for EP2SGX60EF1152I4