EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 29

• Manufacturer Part Number: EP2SGX60EF1152I4
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2186

Altera Corporation
October 2007
This module detects word boundaries for the 8B/10B-based protocols,
SONET, 16-bit, and 20-bit proprietary protocols. This module is also used
to align to specific programmable patterns in PRBS7/23 test mode.
Pattern Detection
The programmable pattern detection logic can be programmed to align
word boundaries using a single 7-, 8-, 10-, 16-, 20, or 32-bit pattern. The
pattern detector can either do an exact match, or match the exact pattern
and the complement of a given pattern. Once the programmed pattern is
found, the data stream is aligned to have the pattern on the LSB portion
of the data output bus.
XAUI, GIGE, PCI Express, and Serial RapidIO standards have embedded
state machines for symbol boundary synchronization. These standards
use K28.5 as their 10-bit programmed comma pattern. Each of these
standards uses different algorithms before signaling symbol boundary
acquisition to the FPGA.
The pattern detection logic searches from the LSB to the most significant
bit (MSB). If multiple patterns are found within the search window, the
pattern in the lower portion of the data stream (corresponding to the
pattern received earlier) is aligned and the rest of the matching patterns
are ignored.
Once a pattern is detected and the data bus is aligned, the word boundary
is locked. The two detection status signals (rx_syncstatus and
rx_patterndetect) indicate that an alignment is complete.
Figure 2–18
Figure 2–18. Word Aligner
is a block diagram of the word aligner.
datain
bitslip
enapatternalign
clock
Aligner
Word
Stratix II GX Device Handbook, Volume 1
patterndetect
syncstatus
dataout
Stratix II GX Architecture
2–21