EP2SGX60EF1152I4 Altera, EP2SGX60EF1152I4 Datasheet - Page 32

• Manufacturer Part Number: EP2SGX60EF1152I4
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152I4

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2186

Transceivers
Figure 2–19. Before and After the Channel Aligner
2–24
Stratix II GX Device Handbook, Volume 1
Lane 3
Lane 3
Lane 2
Lane 1
Lane 0
Lane 1
The rx_syncstatus signal is not available in bit-slipping mode.
Channel Aligner
The channel aligner is available only in XAUI mode and aligns the signals
of all four channels within a transceiver. The channel aligner follows the
IEEE 802.3ae, clause 48 specification for channel bonding.
The channel aligner is a 16-word FIFO buffer with a state machine
controlling the channel bonding process. The state machine looks for an
/A/ (/K28.3/) in each channel, and aligns all the /A/ code groups in the
transceiver. When four columns of /A/ (denoted by //A//) are
detected, the rx_channelaligned signal goes high, signifying that all
the channels in the transceiver have been aligned. The reception of four
consecutive misaligned /A/ code groups restarts the channel alignment
sequence and sends the rx_channelaligned signal low.
Figure 2–19
the aligned channels after the channel aligner.
Lane 0
Lane 2
K
K
K
K
K
K
K
K
K
K
K
shows misaligned channels before the channel aligner and
K
K
K
R
R
R
R
R
K
R
K
A
A
A
A
A
R
A
R
K
K
K
K
K
A
K
A
R
R
R
R
R
K
R
K
R
R
R
R
R
R
R
R
K
K
K
K
K
R
K
R
K
K
K
K
K
K
K
K
R
R
R
R
R
K
R
K
K
K
K
K
K
R
K
R
R
R
R
R
R
Altera Corporation
K
R
K
October 2007
R
R