ADSP-21375KSWZ-2B Analog Devices Inc, ADSP-21375KSWZ-2B Datasheet - Page 9

• Manufacturer Part Number: ADSP-21375KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21375KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (256 kB)
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21375
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Package: 208LQFP EP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 266 MHz
• Ram Size: 64 KB
• Device Million Instructions Per Second: 266 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For the ADSP-21371, the DAI also includes eight serial ports,
four precision clock generators (PCG), and an input data port
(IDP). For the ADSP-21375, the DAI also includes four serial
ports, four precision clock (PCG) and an input data port (IDP).
The IDP provides an additional input path to the core of the
ADSP-21371 processor, configurable as either eight channels of
I
acquisition port.
Each data channel has its own DMA channel that is indepen-
dent from the ADSP-21371/ADSP-21375’s serial ports.
Serial Ports
The ADSP-21371/ADSP-21375 processors feature eight syn-
chronous serial ports for the ADSP-21371; four synchronous
serial ports for the ADSP-21375, that provide an inexpensive
interface to a wide variety of digital and mixed-signal peripheral
devices such as Analog Devices’ AD183x family of audio codecs,
ADCs, and DACs. The serial ports are made up of two data
lines, a clock, and frame sync. The data lines can be pro-
grammed to either transmit or receive and each data line has a
dedicated DMA channel.
For the ADSP-21371, serial ports are enabled via 16 program-
mable pins and simultaneous receive or transmit pins that
support up to 32 transmit or 32 receive channels of audio data
when all eight SPORTs are enabled, or eight duplex TDM
streams of 128 channels per frame.
For the ADSP-21375, serial ports are enabled via eight program-
mable pins and simultaneous receive or transmit pins that
support up to 16 transmit or 16 receive channels of audio data
when all four SPORTs are enabled, or four duplex TDM streams
of 128 channels per frame.
The serial ports operate at a maximum data rate of 50 Mbps.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial ports operate in five modes:
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I
monly used by audio codecs, ADCs, and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
2
S serial data, or a single 20-bit wide synchronous parallel data
• Standard DSP serial mode
• Multichannel (TDM) mode with support for packed I
• I
• Packed I
• Left-justified sample pair mode
mode
2
2
S protocols (I
S mode
2
S mode
2
S is an industry-standard interface com-
Rev. B | Page 9 of 52 | June 2008
2
S
four left-justified sample pair or I
devices) per serial port, with a maximum of up to 32 I
nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I
word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional μ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep-
tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
For the ADSP-21371, the S/PDIF receiver/transmitter has no
separate DMA channels. It receives audio data in serial format
and converts it into a biphase encoded signal. The serial data
input to the receiver/transmitter can be formatted as left justi-
fied, I
24 bits.
For the ADSP-21371, the serial data, clock, and frame sync
inputs to the S/PDIF receiver/transmitter are routed through
the signal routing unit (SRU). They can come from a variety of
sources such as the SPORTs, external pins, the precision clock
generators (PCGs), and are controlled by the SRU control
registers.
The ADSP-21375 does not have an S/PDIF-compatible digital
receiver/transmitter.
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface (SPI) ports, one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers.
Serial Peripheral Interface (Compatible)
The ADSP-21371/ADSP-21375 SHARC processors contain two
serial peripheral interface (SPI) ports. The SPI is an industry-
standard synchronous serial link, enabling the SPI-compatible
ports of the ADSP-21371/ADSP-21375 processors to communi-
cate with other SPI compatible devices. The SPI consists of two
data pins, one device select pin, and one clock pin. It is a full-
duplex synchronous serial interface, supporting both master
and slave modes. The SPI port can operate in a multimaster
environment by interfacing with up to four other SPI-compati-
ble devices, either acting as a master or slave device.
The ADSP-21371/ADSP-21375 SPI-compatible peripheral
implementation also features programmable baud rate and
clock phase and polarities. The ADSP-21371/ADSP-21375 SPI-
compatible port uses open drain drivers to support a multimas-
ter configuration and to avoid data contention.
2
S or right justified with word widths of 16, 18, 20, or
ADSP-21371/ADSP-21375
2
S channels (using two stereo
2
S modes, data-
2
S chan-