ADSP-21375KSWZ-2B Analog Devices Inc, ADSP-21375KSWZ-2B Datasheet - Page 21

• Manufacturer Part Number: ADSP-21375KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21375KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (256 kB)
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21375
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Package: 208LQFP EP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 266 MHz
• Ram Size: 64 KB
• Device Million Instructions Per Second: 266 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Input
Table 16. Clock Input
1
2
Clock Signals
The ADSP-21371/ADSP-21375 can use an external clock or a
crystal. See the CLKIN pin description in
mer can configure the ADSP-21371/ADSP-21375 to use its
internal clock generator by connecting the necessary compo-
nents to CLKIN and XTAL.
connections used for a crystal operating in fundamental mode.
Note that the clock rate is achieved using a 16.67 MHz crystal
and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock
speed of 266 MHz). To achieve the full core clock rate, programs
need to configure the multiplier bits in the PMCTL register.
Parameter
Timing Requirements
t
t
t
t
t
f
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
VCO
CK
CKL
CKH
CKRF
CCLK
CLKIN
2
Figure 6. 266 MHz Operation (Fundamental Mode Crystal)
C1
22pF
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
CLKIN
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
VCO Frequency
16.67 MHz
R1
1M *
Figure 5. Clock Input
Y1
t
CKH
ADSP-2137x
Figure 6
XTAL
shows the component
t
R2
47 *
C2
22pF
CK
t
CKL
Table
6. The program-
Rev. B | Page 21 of 52 | June 2008
266 MHz
Min
22.5
11.25
3.75
11.25
200
1
CCLK
1
1
.
Max
100
45
45
6
10
800
ADSP-21371/ADSP-21375
Unit
ns
ns
ns
ns
ns
MHz