DSPB56374AE Freescale Semiconductor, DSPB56374AE Datasheet - Page 33

• Manufacturer Part Number: DSPB56374AE
• Description: IC DSP 24BIT 150MHZ 52-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56374AE

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (84 kB)
• On-chip Ram: 54kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 150 MIPS
• Maximum Clock Frequency: 150 MHz
• Program Memory Type: Flash
• Program Memory Size: 24 KB
• Data Ram Size: 54 KB
• Operating Supply Voltage: 1.25 V or 3.3 V
• Maximum Operating Temperature: + 110 C
• Mounting Style: SMD/SMT
• Interface Type: SIA, SHI
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Note:
No.
21
22
1
2
3
4
When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will
Periodically sampled and not 100% tested.
RESET duration is measured during the time in which RESET is asserted, V
21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is
recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
be defined by the OMR Bit 6 settings.
For PLL enable, (if bet 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop
requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range
of 0.5 ms.
active and valid. When the V
above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant
power consumption and heat-up. Designs should minimize this state to the shortest possible duration.
Interrupt Requests Rate
DMA Requests Rate
• ESAI, ESAI_1, SHI, Timer
• DMA
• IRQ, NMI (edge trigger)
• IRQ (level trigger)
• Data read from ESAI, ESAI_1, SHI
• Data write to ESAI, ESAI_1, SHI
• Timer
• IRQ, NMI (edge trigger)
Table 20. Reset, Stop, Mode Select, and Interrupt Timing (continued)
RESET
All Pins
Characteristics
1
10
DD
is valid, but the other “required RESET duration” conditions (as specified
DSP56374 Data Sheet, Rev. 4.2
Figure 3. Reset Timing
Reset Value
11
Reset, Stop, Mode Select, and Interrupt Timing
Expression
12 x T
12 x T
8 x T
8 x T
6 x T
7 x T
2 x T
3 x T
C
C
C
C
C
C
C
C
DD
is valid, and the EXTAL input is
13
Min
—
—
—
—
—
—
—
—
V
Max
80.0
53.0
53.0
80.0
40.0
46.7
13.4
20.0
IH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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