DSPB56374AE Freescale Semiconductor, DSPB56374AE Datasheet
DSPB56374AE
Specifications of DSPB56374AE
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DSPB56374AE Summary of contents
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... Freescale Semiconductor, Inc. Symphony™ DSP family, as shown in Significant architectural enhancements include a barrel shifter, 24-bit addressing, and direct memory access © Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007. All rights reserved. Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Features ...
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... Examples: Note: *Values for V 2 Data Sheet Conventions Signal/ Logic State Signal State Symbol PIN True Asserted PIN False Deasserted PIN True Asserted PIN False Deasserted , and V are defined by individual product specifications DSP56374 Data Sheet, Rev. 4.2 Voltage Freescale Semiconductor ...
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... Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25 V • Object Code Compatible with the 56K core • Data ALU with bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmetic support • Program Control with position independent code support Freescale Semiconductor 3 12* Watch ESAI ESAI_1 Triple dog Program ...
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... Memory Sizes (24-bit words) Prog X Data Y Data MS RAM RAM RAM 10K 10K protocols, 10-word receive FIFO, support for 8, 16, and DSP56374 Data Sheet, Rev. 4.2 Prog X Data Y Data ROM ROM ROM 20K 4K 4K 20K 4K 4K 20K 4K 4K 20K 4K 4K 20K 4K 4K Freescale Semiconductor ...
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... Table 2 lists the documents that provide a complete description of the DSP56374 and are required to design properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). ...
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... The user must provide adequate DD power rail. The user must provide adequate DD power rail. The user must provide adequate DD Table 5. Grounds Description DSP56374 Data Sheet, Rev. 4.2 Number of Detailed 1 Signals Description 15 Table 12 3 Table 13 4 Table 14 power rail. DD Freescale Semiconductor ...
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... XTAL Output Chip Driven Crystal Output—Connects the internal Crystal Oscillator output to an external PINIT/NMI Input Input Freescale Semiconductor Table 5. Grounds (continued) Description Table 6. SCAN Signals Signal Description SCAN—Manufacturing test pin. This pin must be connected to ground. Table 7. Clock and PLL Signals Signal Description External Clock / Crystal Input— ...
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... This pin can also be programmed as GPIO. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is de-asserted. This pin has an internal pull up resistor. This input tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... RESET Input 4.6 Serial Host Interface The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I Freescale Semiconductor State during Signal Description Reset Port H2—When the MODC/IRQC is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. ...
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... This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This pin has an internal pull up resistor. This input tolerant. DSP56374 Data Sheet, Rev. 4 bus transactions in the mode, SDA is a Schmitt-trigger input Freescale Semiconductor ...
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... Tri-stated PH4 Input, output, or disconnected Freescale Semiconductor Signal Description SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave ...
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... DACs additional system clock. Port C5—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This pin has an internal pull up resistor. This input tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... PC1 Input, output, or disconnected FST Input or output PC4 Input, output, or disconnected Freescale Semiconductor State during Signal Description Reset GPIO Frame Sync for Receiver—This is the receiver frame sync disconnected input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers ...
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... Port C3—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... Input, output, or disconnected SDO3 Output SDI2 Input PC8 Input, output, or disconnected Freescale Semiconductor State during Signal Description Reset GPIO Serial Data Output 5—When programmed as a transmitter, disconnected SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0—When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register ...
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... TX0 serial transmit shift register. Port C11—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... PE2 Input, output, or disconnected HCKT_1 Input or output PE5 Input, output, or disconnected Freescale Semiconductor State during Signal Description Reset GPIO High Frequency Clock for Receiver—When programmed as disconnected an input, this signal provides a high frequency clock source for the ESAI_1 receiver as an alternate to the DSP core clock ...
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... ESAI_1 transmit clock control register (TCCR_1). Port E4—When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... PE0 Input, output, or disconnected SCKT_1 Input or output PE3 Input, output, or disconnected Freescale Semiconductor State during Signal Description Reset GPIO Receiver Serial Clock_1—SCKR_1 provides the receiver disconnected serial bit clock for the ESAI_1. The SCKR_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0 serial flag 0 pin in the synchronous mode (SYN=1) ...
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... SDI2_1 is used to receive serial data into the RX2 serial receive shift register. Port E8—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input tolerant. DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... Output PE10 Input, output, or disconnected SDO0_1 Output PE11 Input, output, or disconnected Freescale Semiconductor State during Signal Description Reset GPIO Serial Data Output 2—When programmed as a transmitter, disconnected SDO2_1 is used to transmit data from the TX2 serial transmit shift register. Serial Data Input 3—When programmed as a receiver, SDI3_1 is used to receive serial data into the RX3 serial receive shift register ...
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... Port G7—This signal is individually programmable as input, disconnected output, or internally disconnected. Internal Pull down resistor. This input tolerant GPIO Port G8—This signal is individually programmable as input, disconnected output, or internally disconnected. Internal Pull down resistor. This input tolerant DSP56374 Data Sheet, Rev. 4.2 Signal Description Freescale Semiconductor ...
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... PG13 Input, output, or disconnected PG14 Input, output, or disconnected Freescale Semiconductor State During Reset GPIO Port G9—This signal is individually programmable as input, disconnected output, or internally disconnected. Internal Pull down resistor. This input tolerant GPIO Port G10—This signal is individually programmable as input, disconnected output, or internally disconnected ...
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... The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer control/status register (TCSR2). If TIO2 is not being used recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input . DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or V The suggested value for a pullup or pulldown resistor is 4.7 kΩ. Freescale Semiconductor Table 13. Timer Signal (continued) State during ...
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... CORE_VDD, V PLLD_VDD V PLLP_VDD, V IO_VDD PLLA_VDD and GND(Except SCK I JTAG STG = T J DSP56374 Data Sheet, Rev. 4 Value Unit − 0 1.6 − − GND 0 ° 80 LQFP = 105 52 LQFP = 110 − ° +125 2000 200 + θ x Power. Variables used were 85°C A Freescale Semiconductor ...
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... Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Freescale Semiconductor IO_VDD Core_VDD Table 16. Thermal Characteristics Symbol or θ ...
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... Maximum internal supply current is measured DD_IO J = 3.46V 115°C. J DSP56374 Data Sheet, Rev. 4.2 Typ Max Unit 1.25 1.3 V 3.3 3. — V +2V IO_VDD — 0.8 V µA — ± 84 4.7 pF µA — 84 — — V — 0 100 mA 16 — mA 1.2 — mA — Freescale Semiconductor ...
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... Maximum frequency will vary depending on the ordered part number. 11 External Clock Operation The DSP56374 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; an example is shown below. Freescale Semiconductor Table 18. INTERNAL CLOCKS Symbol Min Typ Fref 5 — ...
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... Ohm • drive level of 10 µW ETL ETC + Figure 2. External Clock Timing Table 19. Clock Operation Symbol 1 Eth Etl Etc CYC C Icyc DSP56374 Data Sheet, Rev. 4 Midpoint Min Max Units 3. 3. 6.67 inf ns 50 200 6.67 inf ns 6.67 13.33 Freescale Semiconductor ...
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... A valid clock signal must be applied to the EXTAL pin within the DSP56374 being powered up. Freescale Semiconductor Table 19. Clock Operation (continued) Symbol DSP56374 Data Sheet, Rev. 4.2 External Clock Operation ...
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... DSP56374 Data Sheet, Rev. 4.2 Min Max Unit — — 13.4 — 13.4 — C 2× T 13.4 — C )+T 5.0 — C LOCK 10.0 — 10.0 — 13.4 — 13.4 — — 854 — C 25× T 165 — 5.7 C LOCK ) + LOCK + 3.0 69.0 C Freescale Semiconductor µ ...
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... Designs should minimize this state to the shortest possible duration. RESET All Pins Freescale Semiconductor 1 is valid, but the other “required RESET duration” conditions (as specified DD ...
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... Figure 5. External Interrupt Timing (Negative Edge-Triggered) RESET MODA, MODB, MODC, MODD, PINIT Figure 6. Recovery from Stop State Using IRQA Interrupt Service First Interrupt Instruction Execution 20 b) General Purpose I/O Figure 4. External Fast Interrupt Timing DSP56374 Data Sheet, Rev. 4 IRQA, IRQB, IH IRQC,IRQD, NMI V IL Freescale Semiconductor ...
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... No. Characteristics 23 Minimum serial clock cycle = t XX Tolerable Spike width on data or clock in. 24 Serial clock high period 25 Serial clock low period 26 Serial clock rise/fall time Freescale Semiconductor Mode Filter Mode (min) Master/Slave Bypassed SPICC Very Narrow Narrow Wide — Bypassed Very Narrow ...
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... T 20 — 3 23.2 43.2 — 3 53.2 73.2 — 3 100.0 — — 5 — ns — — 3 26.1 — 90.4 — 110 116.4 — 136 203.4 — 223 2 13.4 — 2 1.6 15 — 2 41.6 55 — 2 91.6 105 — — — 12.0 ns Freescale Semiconductor ...
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... V CORE_VDD 2 Periodically sampled, not 100% tested 3 All times assume noise free inputs. 4 All times assume internal clock frequency of 150 MHz. 5 Equation applies when the result is positive T Freescale Semiconductor Mode Filter Mode Slave Bypassed Very Narrow Narrow Wide Slave Bypassed Very Narrow ...
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... Serial Host Interface SPI Protocol Timing SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 29 MISO (Input) MOSI (Output) 40 HREQ (Input MSB Valid 33 MSB 42 43 Figure 7. SPI Master Timing (CPHA = 0) DSP56374 Data Sheet, Rev. 4 LSB Valid 34 LSB Freescale Semiconductor ...
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... SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 40 HREQ (Input) Freescale Semiconductor MSB Valid 33 MSB Figure 8. SPI Master Timing (CPHA = 1) DSP56374 Data Sheet, Rev. 4.2 Serial Host Interface SPI Protocol Timing LSB Valid 34 LSB 39 ...
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... Serial Host Interface SPI Protocol Timing SS (Input) SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input MISO (Output) 29 MOSI (Input) HREQ (Output MSB 30 MSB Valid 36 Figure 9. SPI Slave Timing (CPHA = 0) DSP56374 Data Sheet, Rev. 4 LSB 29 30 LSB Valid 38 Freescale Semiconductor ...
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... Characteristics XX Tolerable Spike Width on SCL or SDA Filters Bypassed Very Narrow Filters enabled Narrow Filters enabled Wide Fileters enabled. 44 SCL clock frequency 44 SCL clock cycle 45 Bus free time 46 Start condition set-up time Freescale Semiconductor MSB 29 30 MSB Valid Figure 10. SPI Slave Timing (CPHA = 1) 2 Table 22 ...
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... Freescale Semiconductor Unit µs µs µ µs MHz MHz MHz MHz µs µ ...
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... C mode, the user may select a value for the programmed serial clock cycle from 6 × 4096 × T The programmed serial clock cycle (T clock cycle ( shown in SCL Table 23. SCL Serial Clock Cycle (T Nominal Freescale Semiconductor 2 C Protocol Timing (continued) 2 Standard I C Symbol/ 1,2,3,4,5 Expression Min = -40° ...
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... DSP56374 Data Sheet, Rev. 4.2 ACK Stop Min Max Condition 26.4 — 26.4 — 12.8 — 13.4 — 13.4 — 13.4 — — 17 — 7 — 17 — 7 — 19 — 9 — 19 — 9 — 16 — 6 Freescale Semiconductor Unit ...
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... SCKT edge to FST out (wl) low 84 SCKT edge to data out enable from high impedance 85 SCKT edge to transmitter #0 drive enable assertion 86 SCKT edge to data out valid 87 SCKT edge to data out high impedance Freescale Semiconductor Symbol Expression — — — — — — 6 — ...
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... LQFP) / -40°C to 105°C (80 LQFP), C DSP56374 Data Sheet, Rev. 4.2 3 Min Max Condition — 14 — 9 2.0 — 18.0 — 2.0 — 18.0 — 4.0 — 5.0 — — 21.0 — — 14.0 — — 14 — 9 13.4 — C — 18.0 — 18 Freescale Semiconductor 4 Unit ...
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... In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Figure 12 is drawn assuming positive polarity bit clock (TCKP=0) and positive frame sync polarity (TFSP=0). Freescale Semiconductor ...
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... Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In Note: Figure 13 is drawn assuming positive polarity bit clock (RCKP=0) and positive frame sync polarity (RFSP=0 First Bit Figure 13. ESAI Receiver Timing DSP56374 Data Sheet, Rev. 4 Last Bit 75 77 Freescale Semiconductor ...
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... Note: Figure 15 is drawn assuming positive polarity high frequency clock (RHCKP=0) and positive bit clock polarity (RCKP=0). 17 Timer Timing No. Characteristics 98 TIO Low 99 TIO High = 1.25 V ± 0. Note: V CORE_VDD TIO Figure 16. TIO Timer Event Input Restrictions Freescale Semiconductor 95 96 Figure 14. ESAI HCKT Timing 95 97 Figure 15. ESAI HCKR Timing Table 25. Timer Timing Expression 2 × 2 × 2 -40° ...
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... Table 27. JTAG Timing Characteristics × 3); maximum 10 MHz) C DSP56374 Data Sheet, Rev. 4.2 Expression Min Max — 7 — — 0 — 19.7 — 19.7 — C — — 13.0 — — 13 100 101 105 107 All frequencies Unit Min Max — 10.0 MHz Freescale Semiconductor Unit ...
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... TCK low to TDO high impedance Note: = 1.25 V ± 0. CORE_VDD 2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. TCK (Input) 111 Freescale Semiconductor Table 27. JTAG Timing (continued) Characteristics = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP 109 110 V V ...
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... Input Data Valid 114 Output Data Valid 115 114 Output Data Valid Figure 19. Debugger Port Timing Diagram 116 Input Data Valid 118 Output Data Valid 119 118 Output Data Valid DSP56374 Data Sheet, Rev. 4.2 VIH 113 VIH 117 Freescale Semiconductor ...
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... Watchdog Timer Timing No. Characteristics 120 Delay from time-out to fall of TIO1 121 Delay from timer clear to rise of TIO1 Freescale Semiconductor Table 28. Watchdog Timer Timing Expression DSP56374 Data Sheet, Rev. 4.2 Watchdog Timer Timing Min Max Unit 2 × 13.4 — 13.4 — ...
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... SS_HA2 SCK_SCL MISO_SDA MOSI_HA0 GPIO_PG8 GPIO_PG7 IO_Gnd 3 Figure A-1. 80-Pin Vdd Connections DSP56374 Data Sheet, Rev. 4.2 60 SDO5_1_PE6 59 SDO4_1_PE7 58 SDO3_PC8 57 SDO2_PC9 56 SDO1_PC10 55 SDO0_PC11 54 SDO3_1_PE8 53 SDO2_1_PE9 52 Core_Vdd 51 Core_Gnd 50 SDO1_1_PE10 49 SDO0_1_PE11 48 PINIT_NMI 47 IO_Vdd 46 XTAL 45 EXTAL 44 PLLD_Vdd 43 PLLD_Gnd 42 PLLP_Gnd 41 PLLP_Vdd 1.25 V Filter Freescale Semiconductor ...
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... IO_Vdd MODA_IRQA_PH0 MODB_IRQB_PH1 MODC_IRQC_PH2 MODD_IRQD_PH3 Core_Vdd Core_Gnd HREQ_PH4 SS_HA2 SCK_SCL MISO_SDA MOSI_HA0 IO_Gnd 3.3 V Freescale Semiconductor Filter Figure A-2. 52-pin Vdd Connections DSP56374 Data Sheet, Rev. 4.2 Watchdog Timer Timing 39 SDO3_PC8 38 SDO2_PC9 37 SDO1_PC10 36 SDO0_PC11 35 Core_Vdd 34 Core_Gnd 33 PINIT_NMI 32 XTAL 31 EXTAL 30 PLLD_Vdd 29 PLLD_Gnd ...
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... Watchdog Timer Timing A.2 Package Information A.2.1 80-Pin Package 56 . DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... Freescale Semiconductor DSP56374 Data Sheet, Rev. 4.2 Watchdog Timer Timing 57 ...
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... Watchdog Timer Timing 58 DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... Freescale Semiconductor . DSP56374 Data Sheet, Rev. 4.2 Watchdog Timer Timing 59 ...
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... Watchdog Timer Timing A.2.2 52-Pin Package 60 DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... Freescale Semiconductor DSP56374 Data Sheet, Rev. 4.2 Watchdog Timer Timing 61 ...
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... Watchdog Timer Timing 62 DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor ...
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... Freescale Semiconductor DSP56374 Data Sheet, Rev. 4.2 Watchdog Timer Timing 63 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...