ADSP-BF535PKBZ-300 Analog Devices Inc, ADSP-BF535PKBZ-300 Datasheet - Page 8

• Manufacturer Part Number: ADSP-BF535PKBZ-300
• Description: IC DSP CONTROLLER 16BIT 260 BGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF535PKBZ-300

• Interface: PCI, SPI, SSP, UART, USB
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 308kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 260-BGA
• No. Of Bits: 32 Bit
• Frequency: 300MHz
• Supply Voltage: 1.5V
• Embedded Interface Type: PCI, SPI, UART
• No. Of I/o's: 16
• Supply Voltage Range: 0.95V To 1.575V, 3.15V To 3.45V
• Package: 260BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 300 MHz
• Device Million Instructions Per Second: 300 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF535
External Memory Control
The External Bus Interface Unit (EBIU) on the ADSP-BF535
Blackfin processor provides a high performance, glueless
interface to a wide variety of industry-standard memory devices.
The controller is made up of two sections: the first is an SDRAM
controller for connection of industry-standard synchronous
DRAM devices and DIMMs (Dual Inline Memory Module),
while the second is an asynchronous memory controller intended
to interface to a variety of memory devices.
PC133 SDRAM Controller
The SDRAM controller provides an interface to up to four
separate banks of industry-standard SDRAM devices or
DIMMs, at speeds up to f
SDRAM standard, each bank can be configured to contain
between 16M bytes and 128M bytes of memory.
The controller maintains all of the banks as a contiguous address
space so that the processor sees this as a single address space,
even if different size devices are used in the different banks. This
enables a system design where the configuration can be upgraded
after delivery with either similar or different memories.
A set of programmable timing parameters is available to configure
the SDRAM banks to support slower memory devices. The
memory banks can be configured as either 32 bits wide for
maximum performance and bandwidth or 16 bits wide for
minimum device count and lower system cost.
All four banks share common SDRAM control signals and have
their own bank select lines providing a completely glueless
interface for most system configurations.
The SDRAM controller address, data, clock, and command pins
can drive loads up to 50 pF. For larger memory systems, the
SDRAM controller external buffer timing should be selected and
external buffering should be provided so that the load on the
SDRAM controller pins does not exceed 50 pF.
Asynchronous Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O devices.
Each bank can be independently programmed with different
timing parameters, enabling connection to a wide variety of
memory devices including SRAM, ROM, and flash EPROM, as
well as I/O devices that interface with standard memory control
lines. Each bank occupies a 64 Mbyte window in the processor’s
address space but, if not fully populated, these windows are not
made contiguous by the memory controller logic. The banks can
also be configured as 16-bit wide or 32-bit wide buses for ease of
interfacing to a range of memories and I/O devices tailored either
to high performance or to low cost and power.
PCI Interface
The ADSP-BF535 Blackfin processor provides a glueless logical
and electrical, 33 MHz, 3.3 V, 32-bit PCI (Peripheral
Component Interconnect), Revision 2.2 compliant interface.
The PCI interface is designed for a 3 V signalling environment.
The PCI interface provides a bus bridge function between the
SCLK
. Fully compliant with the PC133
–8–
processor core and on-chip peripherals and an external PCI bus.
The PCI interface of the ADSP-BF535 Blackfin processor
supports two PCI functions:
PCI Host Function
As the PCI host, the ADSP-BF535 Blackfin processor provides
the necessary PCI host (platform) functions required to support
and control a variety of off-the-shelf PCI I/O devices (for
example, Ethernet controllers, bus bridges, and so on) in a system
in which the ADSP-BF535 Blackfin processor is the host.
Note that the Blackfin processor architecture defines only
memory space (no I/O or configuration address spaces). The
three address spaces of PCI space (memory, I/O, and configura-
tion space) are mapped into the flat 32-bit memory space of the
ADSP-BF535 Blackfin processor. Because the PCI memory
space is as large as the ADSP-BF535 Blackfin processor memory
address space, a windowed approach is employed, with separate
windows in the ADSP-BF535 Blackfin processor address space
used for accessing the three PCI address spaces. Base address
registers are provided so that these windows can be positioned to
view any range in the PCI address spaces while the windows
remain fixed in position in the ADSP-BF535 Blackfin processor’s
address range.
For devices on the PCI bus viewing the ADSP-BF535 Blackfin
processor’s resources, several mapping registers are provided to
enable resources to be viewed in the PCI address space. The
ADSP-BF535 Blackfin processor’s external memory space,
internal L2, and some I/O MMRs can be selectively enabled as
memory spaces that devices on the PCI bus can use as targets for
PCI memory transactions.
PCI Target Function
As a PCI target device, the PCI host processor can configure the
ADSP-BF535 Blackfin processor subsystem during enumeration
of the PCI bus system. Once configured, the ADSP-BF535
Blackfin processor subsystem acts as an intelligent I/O device.
When configured as a target device, the PCI controller uses the
memory DMA controller to perform DMA transfers as required
by the PCI host.
USB Device
The ADSP-BF535 Blackfin processor provides a USB 1.1
compliant device type interface to support direct connection to
a host system. The USB core interface provides a flexible pro-
grammable environment with up to eight endpoints. Each
endpoint can support all of the USB data types including control,
bulk, interrupt, and isochronous. Each endpoint provides a
memory-mapped buffer for transferring data to the application.
The ADSP-BF535 Blackfin processor USB port has a dedicated
A host to PCI bridge function, in which the ADSP-BF535
Blackfin processor resources (the processor core, internal
and external memory, and the memory DMA controller)
provide the necessary hardware components to emulate
a host computer PCI interface, from the perspective of a
PCI target device.
A PCI target function, in which an ADSP-BF535 Blackfin
processor based intelligent peripheral can be designed to
easily interface to a Revision 2.2 compliant PCI bus.
REV. A