ADSP-BF535PKBZ-300 Analog Devices Inc, ADSP-BF535PKBZ-300 Datasheet - Page 4

• Manufacturer Part Number: ADSP-BF535PKBZ-300
• Description: IC DSP CONTROLLER 16BIT 260 BGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF535PKBZ-300

• Interface: PCI, SPI, SSP, UART, USB
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 308kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 260-BGA
• No. Of Bits: 32 Bit
• Frequency: 300MHz
• Supply Voltage: 1.5V
• Embedded Interface Type: PCI, SPI, UART
• No. Of I/o's: 16
• Supply Voltage Range: 0.95V To 1.575V, 3.15V To 3.45V
• Package: 260BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 300 MHz
• Device Million Instructions Per Second: 300 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF535
The powerful 40-bit shifter has extensive capabilities for perform-
ing shifting, rotating, normalization, extraction, and for
depositing data.
The data for the computational units is found in a multiported
register file of sixteen 16-bit entries or eight 32-bit entries.
A powerful program sequencer controls the flow of instruction
execution, including instruction alignment and decoding. The
sequencer supports conditional jumps and subroutine calls, as
well as zero-overhead looping. A loop buffer stores instructions
locally, eliminating instruction memory accesses for tightly
looped code.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from memory. The DAGs
share a register file containing four sets of 32-bit Index, Modify,
Length, and Base registers. Eight additional 32-bit registers
provide pointers for general indexing of variables and stack
locations.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. Level 2 (L2) memories are other
memories, on-chip or off-chip, that may take multiple processor
cycles to access. At the L1 level, the instruction memory holds
instructions only. The two data memories hold data, and a
dedicated scratch pad data memory stores stack and local variable
information. At the L2 level, there is a single unified memory
space, holding both instructions and data.
In addition, the L1 instruction memory and L1 data memories
may be configured as either Static RAMs (SRAMs) or caches.
The Memory Management Unit (MMU) provides memory pro-
tection for individual tasks that may be operating on the core and
may protect system registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and Emulation mode. User mode has restricted
access to certain system resources, thus providing a protected
software environment, while supervisor mode has unrestricted
access to the system and core resources.
The Blackfin processor instruction set has been optimized so that
16-bit op-codes represent the most frequently used instructions,
resulting in excellent compiled code density. Complex DSP
instructions are encoded into 32-bit op-codes, representing fully
featured multifunction instructions. Blackfin processors support
a limited multiple issue capability, where a 32-bit instruction can
be issued in parallel with two 16-bit instructions, allowing the
programmer to use many of the core resources in a single
instruction cycle.
The Blackfin processor assembly language uses an algebraic
syntax for ease of coding and readability. The architecture has
been optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
Memory Architecture
The ADSP-BF535 Blackfin processor views memory as a single
unified 4 Gbyte address space, using 32-bit addresses. All
resources, including internal memory, external memory, PCI
–4–
address spaces, and I/O control registers, occupy separate
sections of this common address space. The memory portions of
this address space are arranged in a hierarchical structure to
provide a good cost/performance balance with very fast, low
latency memory as cache or SRAM very close to the processor;
and larger, lower cost, and lower performance memory systems
farther away from the processor. See
1
POPULATED SDRAM ARRAY WITH 512M BYTES OF MEMORY. IF ANY BANK
CONTAINS LESS THAN 128M BYTES OF MEMORY, THAT BANK WOULD
EXTEND ONLY TO THE LENGTH OF THE REAL MEMORY SYSTEMS, AND THE
END ADDRESS WOULD BECOME THE START ADDRESS OF THE NEXT BANK.
THIS WOULD CONTINUE FOR ALL FOUR BANKS, WITH ANY REMAINING SPACE
BETWEEN THE END OF MEMORY BANK 3 AND THE BEGINNING OF ASYNC
MEMORY BANK 0, AT ADDRESS 0x2000 0000, TREATED AS RESERVED
ADDRESS SPACE.
0xEEFF FFFC
0xEEFF FF00
0xEEFE FFFF
0xEEFE 0000
0xE7FF FFFF
0x2FFF FFFF
0xFFFF FFFF
THE ADDRESSES SHOWN FOR THE SDRAM BANKS REFLECT A FULLY
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA0 4000
0xFFA0 0000
0xFF90 4000
0xFF90 0000
0xFF80 4000
0xFF80 0000
0xF003 FFFF
0xF000 0000
0xEF00 0000
0xE000 0000
0x2C00 0000
0x2800 0000
0x2400 0000
0x2000 0000
0x1800 0000
0x1000 0000
0x0800 0000
0x0000 0000
Figure 2. Internal/External Memory Map
ASYNC MEMORY BANK 2 (64M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
ASYNC MEMORY BANK 3 (64M BYTE)
ASYNC MEMORY BANK 1 (64M BYTE)
ASYNC MEMORY BANK 0 (64M BYTE)
PCI CONFIG REGISTERS (64K BYTE)
PCI CONFIG SPACE PORT (4 BYTE)
PCI MEMORY SPACE (128M BYTE)
CORE MMR REGISTERS (2M BYTE)
DATA BANK B SRAM (16K BYTE)
DATA BANK A SRAM (16K BYTE)
SCRATCHPAD SRAM (4K BYTE)
L2 SRAM MEMORY (256K BYTE)
INSTRUCTION SRAM (16K BYTE)
SDRAM MEMORY BANK 3
(16M BYTE - 128M BYTE)
PCI IO SPACE (64K BYTE)
SDRAM MEMORY BANK 2
(16M BYTE - 128M BYTE)
SDRAM MEMORY BANK 1
(16M BYTE - 128M BYTE)
SDRAM MEMORY BANK 0
(16M BYTE - 128M BYTE)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Figure
2.
1
1
1
1
REV. A