ADSP-BF535PKBZ-300 Analog Devices Inc, ADSP-BF535PKBZ-300 Datasheet
ADSP-BF535PKBZ-300
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ADSP-BF535PKBZ-300 Summary of contents
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... BYTES L2 SRAM DMA CONTROLLER BOOT ROM 32 32 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel:781/329-4700 Fax:781/326-8703 Blackfin Embedded Processor ADSP-BF535 ® Frequency Multiplier WATCHDOG TIMER REAL-TIME CLOCK UART PORT 0 IrDA UART PORT 1 TIMER0, TIMER1, TIMER2 PROGRAMMABLE FLAGS USB INTERFACE ...
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... ADSP-BF535 TABLE OF CONTENTS GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2 Portable Low Power Architecture . . . . . . . . . . . . . . . 2 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ADSP-BF535 Peripherals . . . . . . . . . . . . . . . . . . . . . 3 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4 Internal (On-Chip) Memory . . . . . . . . . . . . . . . . . . 5 External (Off-Chip) Memory . . . . . . . . . . . . . . . . . 5 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 5 Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Core Event Controller (CEC System Interrupt Controller (SIC Event Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 External Memory Control ...
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... Clock, Programmable Flags, Watchdog Timer, and USB and PCI buses for glueless peripheral expansion. ADSP-BF535 Peripherals The ADSP-BF535 Blackfin processor contains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance. See Functional Block ...
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... C/C++ compiler, resulting in fast and efficient software implementations. Memory Architecture The ADSP-BF535 Blackfin processor views memory as a single unified 4 Gbyte address space, using 32-bit addresses. All resources, including internal memory, external memory, PCI address spaces, and I/O control registers, occupy separate sections of this common address space ...
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... In addition, the PCI interface can either be used as a bridge from the processor core as the controlling CPU in the system host port where another CPU in the system is the host and the ADSP-BF535 is functioning as an intelligent I/O device on the PCI bus. When the ADSP-BF535 Blackfin processor acts as the system ...
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... Booting The ADSP-BF535 Blackfin processor contains a small boot kernel, which configures the appropriate peripheral for booting. If the ADSP-BF535 Blackfin processor is configured to boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see Modes on Page 14 ...
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... Software Interrupt 2 28 Event Control The ADSP-BF535 Blackfin processor provides the user with a very flexible mechanism to control the processing of events. In the CEC, three registers are used to coordinate and control events. Each of the registers is 16 bits wide, and each bit repre- sents a particular event class: CEC Interrupt Latch Register (ILAT)— ...
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... PCI space (memory, I/O, and configura- tion space) are mapped into the flat 32-bit memory space of the ADSP-BF535 Blackfin processor. Because the PCI memory space is as large as the ADSP-BF535 Blackfin processor memory address space, a windowed approach is employed, with separate windows in the ADSP-BF535 Blackfin processor address space used for accessing the three PCI address spaces ...
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... The stopwatch function counts down from a programmed value, with one minute resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the ADSP- BF535 Blackfin processor from a low power state upon generation of any interrupt. ...
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... H.100, H.110, MVIP-90, and HMVIP standards. Serial Peripheral Interface (SPI) Ports The ADSP-BF535 Blackfin processor has two SPI compatible ports that enable the processor to communicate with multiple SPI compatible devices. The SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSIx, and Master Input- Slave Output, MISOx) and a clock pin (Serial Clock, SCKx) ...
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... PFx pin as input or output. Flag Control and Status Registers—Rather than forcing the software to use a read-modify-write process to control the setting of individual flags, the ADSP-BF535 Blackfin processor employs a “write one to set” and “write one to clear” mechanism that allows any combination of individ- ual flags to be set or cleared in a single instruction, without affecting the level of any other flags ...
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... By isolating the internal logic of the ADSP-BF535 Blackfin processor into its own power domain, separate from the PLL, RTC, PCI, and other I/O, the processor can take advantage of dynamic power management, without affecting the PLL, RTC, or other I/O devices ...
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... Timer 0, Timer 1, Timer 2 USB CLK REV. A Clock Signals The ADSP-BF535 Blackfin processor can be clocked by a sine wave input or a buffered shaped clock derived from an external clock oscillator buffered, shaped clock is used, this external clock connects to the processor CLKIN pin. The CLKIN input cannot be halted, changed, or operated below the specified frequency during normal operation ...
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... SSEL1–0 is determined by sampling the SSEL1 and SSEL0 pins during reset. The SSEL value can be changed dynamically by writing the appropriate values to the PLL control register (PLL_CTL), as described in the ADSP-BF535 Blackfin Processor Hardware Reference. Booting Modes The ADSP-BF535 has three mechanisms (listed in automatically loading internal L2 memory after a reset ...
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... File (LDF), allowing the developer to move between the graphical and textual environments. Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the ADSP-BF535 Blackfin processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks ...
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... This document is updated regularly to keep pace with improvements to emulator support. Additional Information This data sheet provides a general overview of the ADSP-BF535 Blackfin processor architecture and functionality. For detailed information on the Blackfin processor family core architecture and instruction set, refer to the ADSP-BF535 Blackfin Processor Hardware Reference and the Blackfin Processor Instruction Set Reference ...
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... PIN DESCRIPTIONS ADSP-BF535 Blackfin processor pin definitions are listed in Table 7. The following pins are asynchronous: ARDY, PF15–0, USB_CLK, NMI, TRST, RESET, PCI_CLK, XTALI, XTALO. Table 7. Pin Descriptions Pin Type Function ADDR25–2 O/T External address bus. DATA31–0 I/O/T External data bus. (Pin has a logic-level hold circuit that prevents the input from floating internally.) ABE3– ...
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... ADSP-BF535 Table 7. Pin Descriptions (continued) Pin Type Function PF4/SPI0SEL2/MSEL4 I/O Programmable flag pin. SPI output select pin. Sensed for configuration state during hardware reset, used to configure the PLL. Selects CK to CLKIN ratio. PF3/SPI1SEL1/MSEL3 I/O Programmable flag pin. SPI output select pin. Sensed for configuration state during hardware reset, used to configure the PLL ...
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... PCI_CLK I PCI clock. PCI_INTA I/O/T PCI interrupt A line on PCI bus. Asserted by the ADSP-BF535 Blackfin processor as a device-to-signal an interrupt to the system processor. Monitored by the ADSP-BF535 when acting as the system processor. PCI_INTB I PCI interrupt B line. Monitored by ADSP-BF535 Blackfin processor when acting as the system processor ...
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... ADSP-BF535 Unused Pins Table 8 shows recommendations for tying off unused pins. All pins that are not listed in the table should be left floating. Table 8. Recommendations for Tying Off Unused Pins Pin Tie Off ARDY V DDEXT BMODE2– GND DDEXT BYPASS V or GND ...
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... V DDEXT max DDEXT max DDEXT max DDEXT MHz 25° 2 –21– ADSP-BF535 Nominal Max 1.6 1.65 1.5 1.575 1.5 1.575 1.5 1.575 3.3 3.45 1.5 1.575 3.3 3.45 3.3 3.45 V +0.5 DDEXT +0.6 V +0.5 DDEXT V V +0.5 DDPCIEXT DDPCIEXT +0.3 ...
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... Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . 200 pF 1 Core Clock: ADSP-BF535PKB-350 . . . . . . . . . . . . . . . . . 350 MHz ADSP-BF535PKB-300 . . . . . . . . . . . . . . . . . 300 MHz ADSP-BF535PBB-300 . . . . . . . . . . . . . . . . . 300 MHz ADSP-BF535PBB-200 . . . . . . . . . . . . . . . . . 200 MHz 1 System Clock (SCLK 133 MHz 1 Storage Temperature Range . . . . . . . . . . –65ºC to +150ºC 1 Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only ...
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... TIMING SPECIFICATIONS Table 9 and Table 10 describe the timing requirements for the ADSP-BF535 Blackfin processor clocks. Take care in selecting MSEL and SSEL ratios so as not to exceed the maximum core clock, system clock and Voltage Controlled Oscillator (VCO) Table 9. Core Clock Requirements Parameter ...
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... ADSP-BF535 Clock and Reset Timing Table 11 and Figure 8 describe clock and reset operations. Per ABSOLUTE MAXIMUM RATINGS on Page tions of CLKIN and clock multipliers must not select core and system clocks in excess of 350/300/200 MHz and 133 MHz, respectively. Table 11. Clock and Reset Timing ...
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... Switching Characteristics t Flag Output Delay with Respect to SCLK DFO t Flag Output Hold After SCLK High HFO SCLK PF (OUTPUT) PF (INPUT) REV DFO HFO FLAG OUTPUT t HFIxS FLAG INPUT Figure 9. Programmable Flags Cycle Timing –25– ADSP-BF535 Min Max Unit 3 SCLK 6.0 ns 6.0 ns ...
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... ADSP-BF535 Timer PWM_OUT Cycle Timing Table 13 and Figure 10 describe timer expired operations. The input signal is asynchronous in “width capture mode” and has an absolute maximum input frequency of f Table 13. Timer PWM_OUT Cycle Timing Parameter Switching Characteristics t Timer Pulse Width Output HTO 1 The minimum time for t ...
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... BE, ADDRESS ADDR25– AWE t SARDY ARDY t ENDAT DATA31–0 WRITE DATA Figure 11. Asynchronous Memory Write Cycle Timing REV ACCESS PROGRAMMED WRITE HOLD EXTENDED ACCESS 2 CYCLES 1 CYCLE 1 CYCLE HARDY t SARDY –27– ADSP-BF535 Min Max 4.0 –1.0 6.0 1.0 7.0 0 DDAT Unit ...
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... ADSP-BF535 Asynchronous Memory Read Cycle Timing Table 15 and Figure 12 describe Asynchronous Memory Read Cycle timing. Table 15. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements t DATA31–0 Setup Before CLKOUT SDAT t DATA31–0 Hold After CLKOUT HDAT t ARDY Setup Before CLKOUT SARDY ...
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... NOTE 1: COMMAND = SRAS, SCAS, SWE, SDQM3–0, SMS, SA10, AND SCKE. REV SCLK t SSDAT t HSDAT t DCAD t ENSDAT t DCAD t HCAD Figure 13. SDRAM Interface Timing –29– ADSP-BF535 Min Max 2.1 2.8 7.5 2.5 2.5 6.0 0.8 6.0 1.0 t SCLKH t SCLKL t DSDAT t HCAD ...
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... ADSP-BF535 Serial Ports Table 17 through Table 22 and Figure 14 timing. Table 17. Serial Ports—External Clock Parameter Timing Requirements t TFS/RFS Setup Before TCLK/RCLK SFSE t TFS/RFS Hold After TCLK/RCLK HFSE t Receive Data Setup Before RCLK SDRE t Receive Data Hold Before RCLK HDRE t TCLK/RCLK Width ...
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... SFSI HFSI RFS t t SDRI HDRI DR SAMPLE EDGE TCLK t t SFSI HFSI TFS DT TCLK/RCLK TCLK/RCLK Figure 14. Serial Ports –31– ADSP-BF535 Min Max 3.0 12.0 2.0 12.0 DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKE t SCLKWE t t DFSE SFSE t t HFSE ...
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... ADSP-BF535 Serial Peripheral Interface (SPI) Port —Master Timing Table 23 and Figure 15 describe SPI port master operations. Table 23. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements t Data Input Valid to SCK Edge (Data Input Setup) SSPID t SCK Sampling Edge to Data Input Invalid ...
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... SPICLS SPICLK t t SPICLS SPICHS t DDSPID t t HDSPID DDSPID MSB t HSPID MSB VALID t DDSPID MSB t SSPID MSB LSB VALID VALID –33– ADSP-BF535 Min Max 2t SCLK 2t SCLK 4t SCLK 2t SCLK 2t SCLK 2t SCLK 1.6 1.6 0.0 6.0 0.0 6.5 0.0 7.0 0.0 6 HDS ...
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... ADSP-BF535 Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 17 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in there is some latency between the generation of internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART ...
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... SCK1, TX0, TX1, TXDPLS, TXDMNS, TXEN, SUSPEND, DEEPSLEEP, PCI_AD31-0, PCI_CBE3-0, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP, PCI_PERR, PCI_PAR, PCI_REQ, PCI_SERR, PCI_RST, PCI_INTA, EMU REV Figure 18. JTAG Port Timing –35– ADSP-BF535 Min Max Unit 20.0 ns 4.0 ns 4.0 ns 4.0 ns 5.0 ns 4.0 ns 7.0 ns 0.0 15 ...
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... Processor executing 75% dual Mac, 25% ADD with moderate data bus activity. 3 Implementation of Enhanced Full Rate (EFR) GSM algorithm. 4 See the ADSP-BF535 Blackfin Processor Hardware Reference Manual for definitions of Sleep and Deep Sleep operating modes specified for when the device is in the reset state. ...
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... C Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate the difference between the ADSP-BF535 Blackfin proces- sor’s output voltage and the input threshold for the device V DDINT requiring the hold time. A typical V will be 0 ...
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... ADSP-BF535 Environmental Conditions The ADSP-BF535 is offered in a 260-ball PBGA package. To determine the junction temperature on the application printed circuit board use CASE JT where Junction temperature ( Case temperature ( C) measured by customer at top CASE center of package. = From Table Power dissipation (see Power Dissipation on Page 36 D method to calculate P ...
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... N18 J09 PCI_AD19 P18 J10 PCI_AD20 L17 J11 PCI_AD21 L16 J12 PCI_AD22 R18 K02 PCI_AD23 T18 K07 PCI_AD24 M17 –39– ADSP-BF535 Signal Pin PCI_AD25 M16 PCI_AD26 N17 PCI_AD27 P17 PCI_AD28 P15 PCI_AD29 N16 PCI_AD30 R17 PCI_AD31 P16 PCI_CBE0 F16 PCI_CBE1 ...
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... ADSP-BF535 Table 29. 260-Ball PBGA Pin Assignment (Alphabetically by Signal) (continued) Signal Pin Signal SWE RFS1 V16 RSCLK0 R13 TCK RSCLK1 U14 TDI RX0 A07 TDO RX1 B08 TFS0 SA10 M01 TFS1 SCAS L03 TMR0 SCK0 U17 TMR1 SCK1 R16 TMR2 SCKE L01 ...
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... DATA0 DDINT GND N03 DATA4 GND N04 V DDINT V N15 V DDINT DDINT V N16 PCI_AD29 DDPCIEXT PCI_AD11 N17 PCI_AD26 –41– ADSP-BF535 Pin Signal R08 PF1/SPISS1/MSEL1 R09 PF5/SPI1SEL2/MSEL5 R10 XTAL1 R11 PF7/SPI1SEL3/DF R12 PF12/SPI0SEL6 R13 RSCLK0 R14 DT0 R15 TFS1 R16 SCK1 R17 ...
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... ADSP-BF535 Table 30. 260-Ball PBGA Pin Assignment (Numerically by Pin Number) (continued) Pin Signal Pin PCI_INTA C14 H17 C15 PCI_PAR H18 PCI_DEVSEL C16 J01 PCI_FRAME C17 J02 PCI_GNT C18 J03 AMS1 D01 J04 D02 ADDR25 J07 D03 ADDR19 J08 D04 ADDR14 J09 D05 ...
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... Figure 25. 260-Ball Metric PBGA Pin Configuration (Top View Figure 26. 260-Ball Metric PBGA Pin Configuration (Bottom View) REV –43– ADSP-BF535 KEY DDRTC DDPLL V V SSRTC SSPLL V GND DDINT V I/O DDEXT V DDPCIEXT KEY: V GND DDINT V I/O DDEXT V V DDPCIEXT DDRTC V V DDPLL SSRTC V SSPLL ...
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... Temperature Range (Ambient) ADSP-BF535PKB-350 0ºC to +70ºC ADSP-BF535PKB-300 0ºC to +70ºC ADSP-BF535PBB-300 –40ºC to +85ºC ADSP-BF535PBB-200 –40ºC to +85ºC Revision History Location 9/04—Data Sheet Changed from REV REV. A Changes to Clock Signals Section ........................................................................................................................ 13 Changes to Recommended Operating Conditions Footnote References ................................................................. 21 Changes to Electrical Characteristics ...