MT47H16M16BG-3 Micron Technology Inc, MT47H16M16BG-3 Datasheet - Page 109

• Manufacturer Part Number: MT47H16M16BG-3
• Manufacturer: Micron Technology Inc

Specifications of MT47H16M16BG-3

• Lead Free Status / Rohs Status: Compliant

REFRESH
Figure 66: Refresh Mode
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
DQS, DQS# 4
Command
Address
Bank
DM 4
DQ 4
CK#
CKE
A10
CK
NOP 1
T0
Notes:
One bank
All banks
Bank(s)
PRE
T1
The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in-
terval of 7.8125µs (MAX) and all rows in all banks must be refreshed at least once every
64ms. The refresh period begins when the REFRESH command is registered and ends
t
ceeds +85°C.
RFC (MIN) later. The average interval must be reduced to 3.9µs (MAX) when T
3
1. NOP commands are shown for ease of illustration; other valid commands may be possi-
2. The second REFRESH is not required and is only shown as an example of two back-to-
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
t CK
ble at these times. CKE must be active during clock positive transitions.
back REFRESH commands.
active (must precharge all active banks).
NOP 1
T2
t CH
t RP
t CL
NOP 1
T3
109
REF
T4
t RFC (MIN)
NOP 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ta0
256Mb: x4, x8, x16 DDR2 SDRAM
REF 2
Ta1
Indicates a break in
time scale
NOP 1
Tb0
©2003 Micron Technology, Inc. All rights reserved.
t RFC 2
NOP 1
Tb1
Don’t Care
REFRESH
C
ex-
Tb2
ACT
RA
RA
BA