MT9HVF6472PY-667F1 Micron Technology Inc, MT9HVF6472PY-667F1 Datasheet
MT9HVF6472PY-667F1
Specifications of MT9HVF6472PY-667F1
Related parts for MT9HVF6472PY-667F1
MT9HVF6472PY-667F1 Summary of contents
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... Frequency/CAS latency – 2.5ns @ (DDR2-800) – 2.5ns @ (DDR2-800) – 3.0ns @ (DDR2-667) – 3.75ns @ (DDR2-533) – 5.0ns @ (DDR2-400 • PCB height – 17.9mm (0.70in) Notes CAS (READ) latency; registered mode 2. Not available in 256MB module density. Data Rate (MT/ – 800 533 800 667 533 – ...
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... Density MT9HVF6472(P)Y-80E__ 512MB MT9HVF6472(P)Y-800__ 512MB MT9HVF6472(P)Y-667__ 512MB MT9HVF6472(P)Y-53E__ 512MB MT9HVF6472(P)Y-40E__ 512MB Table 5: Part Numbers and Timing Parameters – 1GB Modules Base device: MT47H128M8, 1Gb DDR2 SDRAM Module 1 Part Number Density MT9HVF12872(P)Y-80E__ MT9HVF12872(P)Y-800__ MT9HVF12872(P)Y-667__ MT9HVF12872(P)Y-53E__ MT9HVF12872(P)Y-40E__ Notes: 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions ...
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Pin Assignments and Descriptions Table 6: Pin Assignments 240-Pin DDR2 RDIMM Front Pin Symbol Pin Symbol Pin DQ19 61 REF DQ0 33 DQ24 63 4 DQ1 34 DQ25 64 ...
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... LOAD MODE command. Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the SPD EEPROM on the module on the Output Parity error output: Parity error found on the command and address bus. ...
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... Supply Reference voltage: V REF V Supply Ground – No connect: These pins are not connected on the module. RFU – Reserved for future use. PDF: 09005aef81de9391/Source: 09005aef81de9385 HVF9C32_64_128x72.fm - Rev. D 06/08 EN Pin Assignments and Descriptions /2. DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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SR): 240-Pin DDR2 SDRAM VLP RDIMM Functional Block Diagram Figure 2: Functional Block Diagram RS0# DQS0 DQS0# DM0/DQS9 NC/DQS9# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1# DM1/DQS10 NC/DQS10# DQ8 DQ9 DQ10 DQ11 DQ12 ...
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... The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit- wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins ...
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... When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and real- istic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simula- tions to close timing budgets ...
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SR): 240-Pin DDR2 SDRAM VLP RDIMM I Specifications DD Table 10: DDR2 I Specifications and Conditions – 256MB DD Values shown are for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb ...
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SR): 240-Pin DDR2 SDRAM VLP RDIMM Table 11: DDR2 I Specifications and Conditions – 512MB DD Values shown are for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x ...
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SR): 240-Pin DDR2 SDRAM VLP RDIMM Table 12: DDR2 I Specifications and Conditions (Die Revision A) – 1GB DD Values shown are for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb ...
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... DD is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks Value calculated reflects all module ranks in this operating condition PDF: 09005aef81de9391/Source: 09005aef81de9385 HVF9C32_64_128x72 ...
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... Timing and switching specifications for the register listed above are critical for proper oper- ation of the DDR2 SDRAM RDIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC standard JESD82. ...
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SR): 240-Pin DDR2 SDRAM VLP RDIMM Table 15: PLL Specifications CU877 device or equivalent JESD82-8.01 Parameter Symbol DC high-level input V IH voltage DC low-level input V IL voltage V Input voltage (limits high-level ...
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SR): 240-Pin DDR2 SDRAM VLP RDIMM Serial Presence-Detect Table 17: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: ...
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... R 0.80 (0.031) 5.0 (0.197) TYP TYP 63.0 (2.48) TYP 123.0 (4.84) TYP BACK VIEW U11 U10 ® their respective owners. 16 Module Dimensions U6 U7 10.0 (0.394) TYP PIN 120 55.0 (2.16) TYP U12 U13 PIN 121 70.68 (2.78) TYP MAX/MIN or typical (TYP) where noted ...