MT9VDDT6472PHY-335F2 Micron Technology Inc, MT9VDDT6472PHY-335F2 Datasheet - Page 8

• Manufacturer Part Number: MT9VDDT6472PHY-335F2
• Description: MODULE DDR SDRAM 512MB 200SODIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT9VDDT6472PHY-335F2

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.4A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Features: -
• Package / Case: 200-SODIMM
• Lead Free Status / Rohs Status: Compliant

progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
specifies the type of burst (sequential or interleaved),
A4–A6 specify the CAS latency, and A7–A11 (128MB),
A7–A12 (256MB, 512MB), or A7–A13 (1GB) specify the
operating mode.
Burst Length
burst oriented, with the burst length being program-
mable, as shown in Mode Register Diagram. The burst
length determines the maximum number of column
locations that can be accessed for a given READ or
WRITE command. Burst lengths of 2, 4, or 8 locations
are available for both the sequential and the inter-
leaved burst types.
ation or incompatibility with future versions may result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see note 5 of Table 6, Burst Definition
Table, on page 9). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both read and write bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 9.
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS
Latency Diagram, on page 9.
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
Mode register bits A0–A2 specify the burst length, A3
Read and write accesses to the DDR SDRAM are
Reserved states should not be used, as unknown oper-
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
The READ latency is the delay, in clock cycles,
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
8
128MB Module
256MB and 512MB Modules
* M15 and M14 (BA1 and BA0)
* M13 and M12 (BA0 and BA1) must be “0, 0” to select the
* M14 and M13 (BA0 and BA1) must be “0, 0” to select the
1GB Module
0*
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
base mode register (vs. the extended mode register).
base mode register (vs. the extended mode register).
BA1
15
Figure 4: Mode Register Definition
0*
0*
14
BA1
BA0
14
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
0*
13
BA1
13
BA0
A13
13
0*
12
12
BA0
A12 A11
12
A12 A11
Operating Mode
Operating Mode
11
A11
11
11
M13
Operating Mode
0
0
-
10
10
10
A10
A10
A10
M12 M11
0
0
-
9
9
9
A9
A9
A9
0
0
-
8
A8
8
A8
8
A8
M10
0
0
-
Diagram
7
7
7
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
A7 A6 A5 A4 A3
M9
CAS Latency BT
M6
CAS Latency BT
0
0
-
CAS Latency BT
0
0
0
0
1
1
1
1
6
6
6
M8 M7
0
1
M5
-
0
0
1
1
0
0
1
1
5
5
5
0
0
-
M4
©2004 Micron Technology, Inc. All rights reserved.
0
1
0
1
0
1
0
1
4
4
4
M3
M6-M0
0
1
Valid
Valid
3
3
3
-
Burst Length
Burst Length
Burst Length
M2
2
2
2
0
0
0
0
1
1
1
1
A2 A1 A0
A2 A1 A0
CAS Latency
A2 A1 A0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
1
0
0
1
1
0
0
1
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
1
2.5
2
M0
0
1
0
1
0
1
0
1
0
0
0
Interleaved
Burst Type
Sequential
ADVANCE
Burst Length
Mode Register (Mx)
Mode Register (Mx)
Reserved
Reserved
Reserved
Reserved
Reserved
Mode Register (Mx)
M3 = 0
Address Bus
Address Bus
Address Bus
2
4
8