MT9VDDT6472PHY-335F2 Micron Technology Inc, MT9VDDT6472PHY-335F2 Datasheet
MT9VDDT6472PHY-335F2
Specifications of MT9VDDT6472PHY-335F2
Related parts for MT9VDDT6472PHY-335F2
MT9VDDT6472PHY-335F2 Summary of contents
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... Row Addressing DeviceBankAddressing 128Mb (16 Meg x 8) Base Device Configuration Column Addressing Module Rank Addressing pdf: 09005aef808ffe58, source: 09005aef808ffdc7 DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. ...
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... MT9VDDT3272PH(I)G-265_ 256MB MT9VDDT3272PH(I)Y-265_ 256MB 512MB MT9VDDT6472PHG-335_ MT9VDDT6472PHY-335_ 512MB MT9VDDT6472PHG-262_ 512MB MT9VDDT6472PHY-262_ 512MB 512MB MT9VDDT6472PHG-26A_ MT9VDDT6472PHY-26A_ 512MB MT9VDDT6472PH(I)G-265_ 512MB MT9VDDT6472PH(I)Y-265_ 512MB MT9VDDT12872PHG-335_ MT9VDDT12872PHY-335_ MT9VDDT12872PHG-262_ MT9VDDT12872PHY-262_ MT9VDDT12872PHG-26A_ MT9VDDT12872PHY-26A_ MT9VDDT12872PH(I)G-265_ MT9VDDT12872PH(I)Y-265_ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes ...
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... SS DQ35 189 DQ59 40 DQ40 191 193 SDA 44 DD DQ41 195 SCL 46 DQS5 197 V 48 DDSPD V 199 Figure 2: Module Layout Back View U4 U5 PIN 199 PIN 200 Indicates pin Indicates DDQ 3 Pin Assignment (200-Pin SODIMM Back 102 A8 REF DQ23 104 DQ4 ...
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Table 5: Pin Descriptions Refer to Pin Assignment Tables on page 3 for pin number and symbol correlation. PIN NUMBERS SYMBOL 118, 119, 120 WE#, CAS#, RAS# 35, 37 CK0, CK0# 96 CKE0, 121 117, 116 BA0, BA1 99 (A12), ...
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... Input/ Data I/Os: Data bus. Output SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to ...
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... RAS# CAS# CKE0 WE# NOTE: 1. All resistor values are 22 unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part numbering guide at . www micron.com/numberguide. pdf: 09005aef808ffe58, source: 09005aef808ffdc7 DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN 128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR) ...
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... I/O pins. A single read or write access for the DDR SDRAM module effec- tively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corre- sponding n-bit wide, one-half-clock-cycle data trans- fers at the I/O pins ...
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... Figure 4: Mode Register Definition 128MB Module BA1 M13 and M12 (BA0 and BA1) must be “0, 0” to select the base mode register (vs. the extended mode register). 256MB and 512MB Modules BA1 BA0 M14 and M13 (BA0 and BA1) must be “0, 0” to select the base mode register (vs ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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... READ command can be issued. pdf: 09005aef808ffe58, source: 09005aef808ffdc7 DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN 128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR) 200-PIN DDR SDRAM SODIMM Figure 6: Extended Mode Register 128MB Module BA1 BA0 256MB and 512MB Modules BA1 BA0 1GB Module BA1 BA0 A13 The 15 ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 128MB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 13: I Specifications and Conditions – 256MB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 14: I Specifications and Conditions – 512MB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 15: I Specifications and Conditions – 1GB DD DDR SDRAM components only; Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 16: Capacitance) Note: 11; notes appear on pages 19–22 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 17: Electrical Characteristics and Recommended AC Operating Conditions DDR SDRAM components only; ...
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Table 17: Electrical Characteristics and Recommended AC Operating Conditions (Continued) DDR SDRAM components only; notes appear on pages 19–22 AC CHARACTERISTICS PARAMETER DQ-DQS hold, DQS to first non- valid, per access Data Hold Skew Factor ACTIVE to ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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However, an AUTO REFRESH command must be asserted at least once every 140.6µs (128MB) or 70.3µs (256MB, 512MB, 1GB); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The ...
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HP min is the lesser of CL minimum and t minimum actually applied to the device CK and CK# inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not t allowed to be ...
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... DLL is required to be reset. This is followed by 200 clock cycles. 46. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 47. When an input signal is HIGH or LOW defined as a steady state logic HIGH or LOW. ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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... NOTE: 1. The timing and switching specifications for the PLL listed above are critical for proper operation of DDR SDRAM modules. These are meant subset of the parameters for the specific device used on the module. Detailed information for this PLL is available in JEDEC Standard JESD82. ...
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... NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 12, Data Validity, and Figure ...
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Table 19: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 20: EEPROM Operating Modes MODE RW BIT Current Address Read 1 Random Address Read ...
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Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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... Fundamental Memory Type 3 Number of Row Addresses on Ass’y 4 Number of Column Addresses on Ass’y 5 Number of Physical Ranks on DIMM 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels t 9 SDRAM Cycle Time, CK (CAS Latency = 2.5) (see note 2) 10 SDRAM Access from Clock, Latency = 2 ...
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... The value of RP, RCD, and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef808ffe58, source: 09005aef808ffdc7 DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN 128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR) 200-PIN DDR SDRAM SODIMM ENTRY(VERSION ...
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... Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of Physical Ranks on DIMM 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels 9 t SDRAM Cycle Time, CK (CAS Latency = 2.5) (see note 2) 10 SDRAM Access from Clock, (see note 1) ...
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... The value of RP, RCD, and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef808ffe58, source: 09005aef808ffdc7 DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN 128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR) 200-PIN DDR SDRAM SODIMM ENTRY(VERSION) ...
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Figure 16: 200-Pin SODIMM Dimensions 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (0.99) U6 PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Advance: This datasheet contains initial descrip- ...