MT9VDDT6472PHY-335F2 Micron Technology Inc, MT9VDDT6472PHY-335F2 Datasheet - Page 32

• Manufacturer Part Number: MT9VDDT6472PHY-335F2
• Description: MODULE DDR SDRAM 512MB 200SODIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT9VDDT6472PHY-335F2

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.4A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Features: -
• Package / Case: 200-SODIMM
• Lead Free Status / Rohs Status: Compliant

Table 24: Serial Presence- Detect Matrix – 1GB (Continued)
“1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”
NOTE:
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
99-127 Manufacturer-Specific Data ( RSVD)
1. Device latencies used for SPD values.
2. Value for -26A
3. The value of
4. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is
5. The value of
48–61 Reserved
BYTE
36-40 Reserved
65-71 Manufacturer’s JEDEC ID Code (continued)
73-90 Module Part Number (ASCII)
95-98 Module Serial Number
32
33
34
35
41
42
43
44
45
46
47
62
63
64
72
91
92
93
94
represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.
SDRAM device specification is 15ns.
Address and Command Setup Time,
(see note 4)
Address and Command Hold Time,
(see note 4)
Data/Data Mask Input Setup Time,
Data/ Data Mask Input Hold Time,
Min Active Refresh Time
Minimum Auto Refresh to Active/Auto Refresh
Command Period,
SDRAM Device Max Cycle Time,
SDRAM Device Max DQS-DQ Skew Time,
SDRAM Device Max Read Data Hold Skew Factor
Reserved
DIMM Height
SPD Revision
Checksum For Bytes 0-62
Manufacturer’s JEDEC ID Code
Manufacturing Location
PCB Identification Code
Identification Code (Continued)
Year of Manufacture in BCD
Week of Manufacture in BCD
t
t
RAS used for -265 modules is calculated from
RP,
t
CK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.
t
RCD, and
t
RFC
DESCRIPTION
t
RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR
t
RC
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
t
CK
t
t
t
DH
MAX
DS
IH
t
IS
t
DQSQ
32
t
RC -
t
0.75ns (-262/-26A/-265)
RP. Actual device spec value is 40ns.
200-PIN DDR SDRAM SODIMM
1.0ns (-262/-26A/-265)
1.0ns (-262/-26A/-265)
0.5ns (-262/-26A/-265)
0.5ns (-262/-26A/-265)
0.5ns (-262/-26A/-265)
13ns (-262/-26A/-265)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ENTRY(VERSION)
65ns (-265/-26A)
60ns (-335/-262)
0.45ns (-335)
0.55ns (-335)
0.45ns (-335
0.45ns (-335
Revision 1.0
0.8ns (-335)
0.8ns (-335)
12ns (-335)
MICRON
120ns
01–12
-26A
-335
-262
-265
1–9
0
©2004 Micron Technology, Inc. All rights reserved.
MT9VDDT12872PH
Variable Data
Variable Data
Variable Data
Variable Data
01–0C
01–09
A0
A0
3C
2D
C0
ED
1D
2C
80
80
45
50
45
50
00
41
78
30
34
32
55
75
00
01
00
10
30
00
00
–
ADVANCE