MT9HTF6472PKY-40EB1 Micron Technology Inc, MT9HTF6472PKY-40EB1 Datasheet - Page 7

• Manufacturer Part Number: MT9HTF6472PKY-40EB1
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472PKY-40EB1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.035A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

General Description
Register and PLL EEPROM Operation
Serial Presence-Detect EEPROM Operation
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C64_128x72K.fm - Rev. D 7/08 EN
The MT9HTF6472(P)K and MT9HTF12872(P)K DDR2 SDRAM modules are high-speed,
CMOS dynamic random access 512MB and 1GB memory modules organized in x72
configurations. These modules use 512Mb DDR2 SDRAM devices with four internal
banks, or 1Gb DDR2 SDRAM device with eight internal banks.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-
wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
These DDR2 SDRAM modules operate in registered mode, where the command/address
input signals are latched in the registers on the rising clock edge and sent to the DDR2
SDRAM devices on the following rising clock edge (data access is delayed by one clock
cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock
signals (CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce clock,
control, command, and address signals loading by isolating DRAM from the system
controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the
JEDEC clock reference board. Registered mode will add one clock cycle to CL.
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various SDRAM organizations and timing parameters. The remaining 128 bytes
of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I
which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected
to V
2
C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],
SS
, permanently disabling hardware write protect.
512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2005 Micron Technology, Inc. All rights reserved.