MT9HTF6472PKY-40EB1 Micron Technology Inc, MT9HTF6472PKY-40EB1 Datasheet - Page 4

• Manufacturer Part Number: MT9HTF6472PKY-40EB1
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472PKY-40EB1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.035A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

Table 6:
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C64_128x72K.fm - Rev. D 7/08 EN
RAS#, CAS#, WE#
CK0, CK0#
RDQS[8:0]
V
DQS#[8:0]
DQS[8:0],
DQ[63:0]
Symbol
E
DM[8:0]
EVENT#
BA[2:0]
DD
A[15:0]
RESET#
SA[2:0]
CB[7:0]
P
RR
ODT0
CKE0
SDA
AR
S0#
SCL
/V
_O
_I
DD
UT
N
Q
Pin Descriptions
Output
Output
Supply
(open
drain)
(open
drain)
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA[2/1:0]) or all device banks (A10 HIGH). The address inputs also provide the
op-code during a LOAD MODE command. A[13:0] (512MB, 1GB). A[15:14] are connected for
parity.
Bank address inputs: BA[2/1:0] define the device bank to which an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA[2/1:0] define which mode register (MR,
EMR1, EMR2, and EMR3) is loaded during the LOAD MODE command. BA[1:0] (512MB) and
BA[2:0] (1GB).
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DDR2 SDRAM.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of DQS. Although the DM pins are input-only, DM loading is designed to match
that of the DQ and DQS pins. If RDQS is disabled, RDQS[8:0] become DM[8:0] and
RDQS#[8:0] are not used.
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will
be ignored if disabled via the LOAD MODE command.
Parity input: Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: These pins are used to configure the SPD EEPROM address range on
the I
Serial clock for SPD EEPROM: SCL is used to synchronize communication to and from the
SPD EEPROM.
Check bits.
Data input/output: Bidirectional data bus.
Data strobe: DQS# is only used when differential data strobe mode is enabled via the
LOAD MODE command. Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of
the SPD EEPROM on the module on the I
Parity error output: Parity error found on the command and address bus.
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded.
Power supply: 1.8V ±0.1V. The component V
V
DD
.
2
C bus.
512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
4
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
C bus.
Pin Assignments and Descriptions
DD
and V
DD
Q are connected to the module
©2005 Micron Technology, Inc. All rights reserved.