ADC083000CIYB/NOPB National Semiconductor, ADC083000CIYB/NOPB Datasheet - Page 35

• Manufacturer Part Number: ADC083000CIYB/NOPB
• Description: IC ADC 8BIT 3GSPS LP 128-LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC083000CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 3G
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 2.3W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC083000CIYB; *ADC083000CIYB/NOPB; ADC083000CIYB

return to normal operation, the pipeline will contain meaning-
less information and must be flushed.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state.
2.5 THE DIGITAL OUTPUTS
The ADC083000 demultiplexes the output data of each of the
two ADCs on the die onto two LVDS output buses (total of
four buses, two for each ADC). For each of the two converters,
the results of successive conversions start on the falling
edges of the CLK+ pin and are available on one of the two
LVDS buses. The results of conversions that start on the ris-
ing edges of the CLK+ pin are available on the other LVDS
bus. This means that the word rate at each LVDS bus is 1/2
the ADC083000 input clock rate and the two buses must be
multiplexed to obtain the entire 3 GSPS conversion result.
Since the minimum recommended input clock rate for this
device is 500 MHz, the sampling rate can be reduced to as
low as 1 GSPS by using the results available on all four LVDS
busses. The effective sampling rate can be reduced to as low
as 250 MSPS by decimating the data by using one bus and
a 500MHz clock.
There is one LVDS output clock pair (DCLK+/-) available for
use to latch the LVDS outputs on all buses. Whether the data
is sent at the rising or falling edge of DCLK is determined by
the sense of the OutEdge pin, as described in Section 2.4.3.
DDR (Double Data Rate) clocking can also be used. In this
mode a word of data is presented with each edge of DCLK,
reducing the DCLK frequency to 1/4 the input clock frequency.
When the device is in DDR mode, register address 1h, bit 8
must be set to 0b. See the Timing Diagram section for details.
The OutV pin is used to set the LVDS differential output levels.
See Section 2.4.4.
The output format is Offset Binary. Accordingly, a full-scale
input level with V
an output code of all ones, a full-scale input level with V
positive with respect to V
zeros and when V
be 128.
2.6 POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A 33 µF
capacitor should be placed within an inch (2.5 cm) of the A/D
converter power pins. A 0.1 µF capacitor should be placed as
close as possible to each V
centimeter. Leadless chip capacitors are preferred because
they have low lead inductance.
The V
other to prevent any digital noise from being coupled into the
analog portions of the ADC. A ferrite choke, such as the JW
Miller FB20009-3B, is recommended between these supply
lines when a common source is used for them.
As is the case with all high speed converters, the ADC083000
should be assumed to have little power supply noise rejection.
Any power supply used for digital circuitry in a system where
a lot of digital power is being consumed should not be used
to supply power to the ADC083000. The ADC supplies should
be the same supply used for other analog circuitry, if not a
dedicated supply.
A
and V
DR
IN
supply pins should be isolated from each
IN
+ positive with respect to V
+ and V
IN
+ will produce an output code of all
IN
A
− are equal, the output code will
pin, preferably within one-half
IN
− will produce
IN
−
35
2.6.1 Supply Voltage
The ADC083000 is specified to operate with a supply voltage
of 1.9V ±0.1V. It is very important to note that, while this de-
vice will function with slightly higher supply voltages, these
higher supply voltages may reduce product lifetime.
No pin should ever have a voltage on it that is in excess of the
supply voltage or below ground by more than 150 mV, not
even on a transient basis. This can be a problem upon appli-
cation of power and power shut-down. Be sure that the sup-
plies to circuits driving any of the input pins, analog or digital,
do not come up any faster than does the voltage at the
ADC083000 power pins.
The Absolute Maximum Ratings should be strictly observed,
even during power up and power down. A power supply that
produces a voltage spike at turn-on and/or turn-off of power
can destroy the ADC083000. The circuit of Figure 15 will pro-
vide supply overshoot protection.
Many linear regulators will produce output spiking at power-
on unless there is a minimum load provided. Active devices
draw very little current until their supply voltages reach a few
hundred millivolts. The result can be a turn-on spike that can
destroy the ADC083000, unless a minimum load is provided
for the supply. The 100Ω resistor at the regulator output of
Figure 15 provides a minimum output current during power-
up to ensure there is no turn-on spiking. Whether a linear or
switching regulator is used, it is advisable to provide a slow
start circuit to prevent overshoot of the supply.
In the circuit of Figure 15, an LM317 linear regulator is satis-
factory if its input supply voltage is 4V to 5V . If a 3.3V supply
is used, an LM1086 linear regulator is recommended.
The output drivers should have a supply voltage, V
within the range specified in the Operating Ratings table. This
voltage should not exceed the V
never spike to a voltage greater than ( V
If the power is applied to the device without an input clock
signal present, the current drawn by the device might be be-
low 200 mA. This is because the ADC083000 gets reset
through clocked logic and its initial state is unknown. If the
reset logic comes up in the "on" state, it will cause most of the
analog circuitry to be powered down, resulting in less than
100 mA of current draw. This current is greater than the power
down current because not all of the ADC is powered down.
The device current will be normal after the input clock is es-
tablished.
2.6.2 Thermal Management
The ADC083000 is capable of impressive speeds and per-
formance at very low power levels for its speed. However, the
power consumption is still high enough to require attention to
thermal management. For reliability reasons, the die temper-
ature should be kept to a maximum of 130°C. That is, T
(ambient temperature) plus ADC power consumption times
θ
JA
(junction to ambient thermal resistance) should not ex-
FIGURE 15. Non-Spiking Power Supply
A
supply voltage and should
A
+ 100mV).
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