ADC083000CIYB/NOPB National Semiconductor, ADC083000CIYB/NOPB Datasheet - Page 24

• Manufacturer Part Number: ADC083000CIYB/NOPB
• Description: IC ADC 8BIT 3GSPS LP 128-LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC083000CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 3G
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 2.3W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC083000CIYB; *ADC083000CIYB/NOPB; ADC083000CIYB

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1.0 Functional Description
The ADC083000 is a versatile A/D Converter with an innova-
tive architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section.
While it is generally poor practice to allow an active pin to float,
pins 4 and 14 of the ADC083000 are designed to be left float-
ing without jeopardy. In all discussions throughout this data
sheet, whenever a function is called by allowing a control pin
to float, connecting that pin to a potential of one half the V
supply voltage will have the same effect as allowing it to float.
1.1 OVERVIEW
The ADC083000 uses a calibrated folding and interpolating
architecture that achieves 7.2 effective bits. The use of folding
amplifiers greatly reduces the number of comparators and
power consumption. Interpolation reduces the number of
front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to other things, on-chip calibration reduces the INL bow often
seen with folding architectures. The result is an extremely
fast, high performance, low power converter.
The analog input signal that is within the converter's input
voltage range is digitized to eight bits at speeds of 1.0 GSPS
to 3.0 GSPS, typical. Differential input voltages below nega-
tive full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at the analog input will cause the OR (Out of
Range) output to be activated. This single OR output indicates
when the output code from the converter is below negative
full scale or above positive full scale.
The ADC083000 demultiplexes the data at 1:4 and is output
on all four output busses at a quarter of the ADC sampling
rate. The outputs must be interleaved by the user to provide
output words at the full conversion rate.
The output levels may be selected to be normal or reduced
voltage. Using reduced levels saves power but could result in
erroneous data capture of some or all of the bits, especially
at higher sample rates and in marginally designed systems.
1.1.1 Calibration
A calibration is performed upon power-up and can also be
invoked by the user upon command. Calibration trims the
100Ω analog input differential termination resistor and mini-
mizes full-scale error, offset error, DNL and INL, resulting in
maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal
bias currents are also set with the calibration process. All of
this is true whether the calibration is performed upon power
up or is performed upon command. Running the calibration is
an important part of this chip's functionality and is required in
order to obtain adequate performance. In addition to the re-
quirement to be run at power-up, calibration must be re-run
by the user whenever the state of the FSR pin is changed. For
best performance, we recommend an on command calibra-
tion be run after initial power up and the device has reached
a stable temperature. Also, we recommend that an on com-
mand calibration be run whenever the operating temperature
changes significantly relative to the specific system perfor-
mance requirements. See Section 2.4.2.2 for more informa-
tion. Calibration can not be initiated or run while the device is
in the power-down mode. See Section 1.1.7 for information
on the interaction between Power Down and Calibration.
A
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In normal operation, calibration is performed just after appli-
cation of power and whenever a valid calibration command is
given, which is holding the CAL pin low for at least 80 input
clock cycles, then hold it high for at least another 80 input
clock cycles. The time taken by the calibration procedure is
specified in the A.C. Characteristics Table. Holding the CAL
pin high during power up will prevent the calibration process
from running until the CAL pin experiences the above-men-
tioned 80 input clock cycles low followed by 80 cycles high.
CalDly (pin 127) is used to select one of two delay times after
the application of power to the start of calibration. This cali-
bration delay is 2
GSPS) with CalDly low, or 2
seconds at 3 GSPS) with CalDly high. These delay values
allow the power supply to come up and stabilize before cali-
bration takes place. If the PD pin is high upon power-up, the
calibration delay counter will be disabled until the PD pin is
brought low. Therefore, holding the PD pin high during power
up will further delay the start of the power-up calibration cycle.
The best setting of the CalDly pin depends upon the power-
on settling time of the power supply.
The CAL bit does not reset itself to zero automatically, but
must be manually reset before another calibration event can
be initiated. If no further calibration event is desired, the CAL
bit may be left high indefinitely, with no negative conse-
quences. The RTD bit setting is critical for running a calibra-
tion event with the Clock Phase Adjust enabled. If initiating a
calibration event while the Clock Phase Adjust is enabled, the
RTD bit must be set to high, or no calibration will occur. If
initiating a calibration event while the Clock Phase Adjust is
not enabled, a normal calibration will occur, regardless of the
setting of the RTD bit.
Calibration Operation Notes:
•
•
•
1.1.2 Acquiring the Input
Data is acquired at both the rising and falling edges of CLK
(pin 10) and the digital equivalent of that data is available at
the digital outputs 13 input clock cycles later for the Dd output
bus, 13.5 input clock cycles later for Dc output bus, 14 input
clock cycles later for the Db output bus and 14.5 input clock
cycles later for the Da output bus. See Table 1. There is an
additional internal delay called t
at the outputs. See Figure 3 and Figure 4.
During the calibration cycle, the OR output may be active
as a result of the calibration algorithm. All data on the
output pins and the OR output are invalid during the
calibration cycle.
During the power-up calibration and during the on-
command calibration when Resistor Trim Disable
(address: 1h, bit 13) is not active (0b) , all clocks are halted
on chip, including internal clocks and DCLK, while the
input termination resistor is trimmed to a value that is equal
to R
resistor calibration portion of the calibration cycle. See
Section 2.4.2.2 for information on maintaining DCLK
operation during on-command calibration.
R
3300 Ω ±0.1%. With this value, the input termination
resistor is trimmed to be 100 Ω. Because R
to set the proper current for the Track and Hold amplifier,
for the preamplifiers and for the comparators, other values
of R
The CalRun output is high whenever the calibration
procedure is running. This is true whether the calibration
is done at power-up or on-command.
EXT
EXT
EXT
is located between pin 32 and ground and must be
/ 33. This is to reduce noise during the input
should not be used.
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input clock cycles (about 22 ms at 3
31
OD
input clock cycles (about 1.4
before the data is available
EXT
is also used