ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 33

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

2.0 Applications Information
To use this feature in the non-enhanced control mode, allow
pin 127 to float and the signal at the "I" channel input will be
sampled by both converters. The Calibration Delay will then
only be a short delay.
In the enhanced control mode, either input may be used for
dual edge sampling. See Section 1.1.5.1.
IMPORTANT NOTES:
1) For the Extended Control Mode - When using the Auto-
matic Clock Phase Control feature in dual edge sampling
mode, it is important that the automatic phase control is
disabled (set bit 14 of DES Enable register Dh to 0) before
the ADC is powered up. Not doing so may cause the device
not to wakeup from the powerdown state.
2) For the Non-Extended Control Mode - When the
ADC08D1000 is powered up and DES mode is required,
ensure that pin 127 (CalDly/DES/SCS) is initially pulled low
during or after the power up sequence. The pin can then be
allowed to float or be tied to V
This will ensure that the part enters the DES mode correctly.
3) The automatic phase control should also be disabled if the
input clock is interrupted or stopped for any reason.This is
also the case if a large abrupt change in the clock frequency
occurs.
4) If a calibration of the ADC is required in Auto DES mode,
the device must be returned to the Normal Mode of operation
before performing a calibration cycle. Once the Calibration
has been completed, the device can be returned to the Auto
DES mode and operation can resume.
2.4.6 Power Down Feature
The Power Down pins (PD and PDQ) allow the ADC08D500
to be entirely powered down (PD) or the "Q" channel to be
powered down and the "I" channel to remain active. See
Section 1.1.7 for details on the power down feature.
The digital data (+/-) output pins are put into a high imped-
ance state when the PD pin for the respective channel is
high. Upon return to normal operation, the pipeline will con-
tain meaningless information and must be flushed.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration
sequence until the PD input goes low. If a manual calibration
is requested while the device is powered down, the calibra-
tion will not begin at all. That is, the manual calibration input
is completely ignored in the power down state.
2.5 THE DIGITAL OUTPUTS
The ADC08D1000 demultiplexes the output data of each of
the two ADCs on the die onto two LVDS output buses (total
of four buses, two for each ADC). For each of the two
converters, the results of successive conversions started on
the odd falling edges of the CLK+ pin are available on one of
the two LVDS buses, while the results of conversions started
on the even falling edges of the CLK+ pin are available on
the other LVDS bus. This means that, the word rate at each
LVDS bus is 1/2 the ADC08D1000 input clock rate and the
two buses must be multiplexed to obtain the entire 1 GSPS
conversion result.
Since the minimum recommended input clock rate for this
device is 200 MSPS (normal non DES mode), the effective
rate can be reduced to as low as 100 MSPS by using the
(Continued)
A
/ 2 to enter the DES mode.
33
results available on just one of the the two LVDS buses and
a 200 MHz input clock, decimating the 200 MSPS data by
two.
There is one LVDS output clock pair (DCLK+/-) available for
use to latch the LVDS outputs on all buses. Whether the data
is sent at the rising or falling edge of DCLK is determined by
the sense of the OutEdge pin, as described in Section 2.4.3.
DDR (Double Data Rate) clocking can also be used. In this
mode a word of data is presented with each edge of DCLK,
reducing the DCLK frequency to 1/4 the input clock fre-
quency. See the Timing Diagram section for details.
The OutV pin is used to set the LVDS differential output
levels. See Section 2.4.4.
The output format is Offset Binary. Accordingly, a full-scale
input level with V
duce an output code of all ones, a full-scale input level with
V
code of all zeros and when V
output code will vary between codes 127 and 128.
2.6 POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A 33
µF capacitor should be placed within an inch (2.5 cm) of the
A/D converter power pins. A 0.1 µF capacitor should be
placed as close as possible to each V
one-half centimeter. Leadless chip capacitors are preferred
because they have low lead inductance.
The V
other to prevent any digital noise from being coupled into the
analog portions of the ADC. A ferrite choke, such as the JW
Miller FB20009-3B, is recommended between these supply
lines when a common source is used for them.
As is the case with all high speed converters, the
ADC08D500 should be assumed to have little power supply
noise rejection. Any power supply used for digital circuitry in
a syatem where a lot of digital power is being consumed
should not be used to supply power to the ADC08D500. The
ADC supplies should be the same supply used for other
analog circuitry, if not a dedicated supply.
2.6.1 Supply Voltage
The ADC08D500 is specified to operate with a supply volt-
age of 1.9V
device will function with slightly higher supply voltages,
these higher supply voltages may reduce product lifetime.
No pin should ever have a voltage on it that is in excess of
the supply voltage or below ground by more than 150 mV,
not even on a transient basis. This can be a problem upon
application of power and power shut-down. Be sure that the
supplies to circuits driving any of the input pins, analog or
digital, do not come up any faster than does the voltage at
the ADC08D500 power pins.
The Absolute Maximum Ratings should be strictly observed,
even during power up and power down. A power supply that
produces a voltage spike at turn-on and/or turn-off of power
can destroy the ADC08D500. The circuit of Figure 15 will
provide supply overshoot protection.
Many linear regulators will produce output spiking at
power-on unless there is a minimum load provided. Active
devices draw very little current until their supply voltages
reach a few hundred millivolts. The result can be a turn-on
spike that can destroy the ADC08D500, unless a minimum
IN
− positive with respect to V
A
and V
±
0.1V. It is very important to note that, while this
DR
IN
supply pins should be isolated from each
+ positive with respect to V
IN
IN
+ and V
+ will produce an output
A
pin, preferably within
IN
− are equal, the
IN
www.national.com
− will pro-