ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 32

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

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2.0 Applications Information
Full-Scale Input Range setting, Self Calibration, Calibration
Delay, Output Edge Synchronization choice, LVDS Output
Level choice and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
The input full-scale range can be selected to be either 650
mV
(pin 14) in the Normal Mode of operation. In the Extended
Control Mode, the input full-scale range may be set to be
anywhere from 560 mV
more information.
2.4.2 Self Calibration
The ADC08D500 self-calibration must be run to achieve
specified performance. The calibration procedure is run
upon power-up and can be run any time on command. The
calibration procedure is exactly the same whether there is a
clock present upon power up or if the clock begins some time
after application of power. The CalRun output indicator is
high while a calibration is in progress.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D500 will function with the CAL pin held
high at power up, but no calibration will be done and perfor-
mance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See
On-Command Calibration Section 2.4.2.2.
The internal power-on calibration circuitry comes up in an
unknown logic state. If the clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
2.4.2.2 On-Command Calibration
An on-command calibration may be run at any time in NOR-
MAL (non-DES) mode only. Do not run a calibration while
operating the ADC in Auto DES Mode.
If the ADC is operating in Auto DES mode and a calibration
cycle is required then the controlling application should bring
the ADC into normal (non DES) mode before an On Com-
mand calibration is initiated. Once calibration has completed,
the ADC can be put back into Auto DES mode.
To initiate an on-command calibration, bring the CAL pin high
for a minimum of 80 input clock cycles after it has been low
for a minimum of 80 input clock cycles. Holding the CAL pin
high upon power up will prevent execution of power-on
calibration until the CAL pin is low for a minimum of 80 input
clock cycles, then brought high for a minimum of another 80
input clock cycles. The calibration cycle will begin 80 input
clock cycles after the CAL pin is thus brought high. The
CalRun signal should be monitored to determine when the
calibration cycle has completed.
The minimum 80 input clock cycle sequences are required to
ensure that random noise does not cause a calibration to
(Continued)
P-P
or 870 mV
P-P
, as selected with the FSR control input
P-P
to 840 mV
P-P
. See Section 2.2 for
32
begin when it is not desired. As mentioned in section 1.1.1
for best performance, a self calibration should be performed
20 seconds or more after power up and repeated when the
operating temperature changes significantly according to the
particular system performance requirements. ENOB drops
slightly as junction temperature increases and executing a
new self calibration cycle will essentially eliminate the
change.
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in Section 1.1.1. The calibration delay values
allow the power supply to come up and stabilize before
calibration takes place. With no delay or insufficient delay,
calibration would begin before the power supply is stabilized
at its operating value and result in non-optimal calibration
coefficients. If the PD pin is high upon power-up, the calibra-
tion delay counter will be disabled until the PD pin is brought
low. Therefore, holding the PD pin high during power up will
further delay the start of the power-up calibration cycle. The
best setting of the CalDly pin depends upon the power-on
settling time of the power supply.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these clock signals. That is, the
output data transition can be set to occur with either the
rising edge or the falling edge of the DCLK signal, so that
either edge of that clock signal can be used to latch the
output data into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchro-
nized with (changes with) the rising edge of the DCLK+ (pin
82). When OutEdge is low, the output data is synchronized
with the falling edge of DCLK+.
At the very high speeds of which the ADC08D500 is capable,
slight differences in the lengths of the clock and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on
the DCLK edge that best suits the application circuit and
layout.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
For short LVDS lines and low noise systems, satisfactory
performance may be realized with the FSR input low. If the
LVDS lines are long and/or the system in which the
ADC08D500 is used is noisy, it may be necessary to tie the
FSR pin high.
2.4.5 Dual Edge Sampling
The Dual Edge Sampling (DES) feature causes one of the
two input pairs to be routed to both ADCs. The other input
pair is deactivated. One of the ADCs samples the input
signal on one clock edge, the other samples the input signal
on the other clock edge. The result is a 1:4 demultiplexed
output with a sample rate that is twice the input clock fre-
quency.