ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 26

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

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1.0 Functional Description
The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 3.
1.3 THE SERIAL INTERFACE
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS) Eight write only registers are acces-
sible through this serial interface.
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times
with respect to the SCLK must be observed.
SCLK: Serial data input is accepted with the rising edge of
this signal.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be
observed. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in Figure
5 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading
sequence is such that a 0b is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register
that is to be written to and the last 16 bits are the data written
to the addressed register. The addresses of the various
registers are indicated in Table 4.
Refer to the Register Description (Section 1.4) for informa-
tion on the data to be written to the registers.
Subsequent register accesses may be performed immedi-
ately, starting with the 33rd SCLK. This means that the SCS
input does not have to be de-asserted and asserted again
between register addresses. It is possible, although not rec-
ommended, to keep the SCS input permanently enabled (at
a logic low) when using extended control.
IMPORTANT NOTE: The Serial Interface should not be
used when calibrating the ADC. Doing so will impair the
performance of the device until it is re-calibrated correctly.
Programming the serial registers will also reduce dynamic
performance of the ADC for the duration of the register
access time.
TABLE 3. Extended Control Mode Operation (Pin 14
LVDS Output Amplitude
SDR or DDR Clocking
Dual Edge Sampling
Input Offset Adjust
DDR Clock Phase
Calibration Delay
Full-Scale Range
Feature
(DES)
Floating)
Extended Control Mode
Data changes with DCLK
700 mV nominal for both
No adjustment for either
Normal amplitude
edge (0˚ phase)
DDR Clocking
Default State
(710 mV
Not enabled
Short Delay
channels
channel
P-P
(Continued)
)
26
1.4 REGISTER DESCRIPTION
Eight write-only registers provide several control and con-
figuration options in the Extended Control Mode. These reg-
isters have no effect when the device is in the Normal
Control Mode. Each register description below also shows
the Power-On Reset (POR) state of each control bit.
Bit 15
Bit 14
Bit 13
Bit 12
A3
Addr: 1h (0001b)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D15
D7
1
1
D14
A2
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
Must be set to 1b
Must be set to 0b
Must be set to 1b
DCS: Duty Cycle Stabilizer. When this bit is
set to 1b, a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disbaled.
A3 loaded after H0, A0 loaded last
TABLE 4. Register Addresses
D13
Configuration Register
D5
A1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Loading Sequence:
4-Bit Address
DCS DCP
D12
D4
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D11
D3
1
Hex
Ah
Bh
Ch
Dh
Eh
Fh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
nDE
D10
D2
W only (0xB2FF)
1
"Q" Ch Full-Scale
DES Fine Adjust
"I" Ch Full-Scale
Voltage Adjust
Voltage Adjust
"Q" Ch Offset
Configuration
"I" Ch Offset
DES Coarse
DES Enable
Addressed
OV
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
D9
D1
Register
1
Adjust
OE
D8
D0
1