AD7192BRUZ Analog Devices Inc, AD7192BRUZ Datasheet - Page 26

• Manufacturer Part Number: AD7192BRUZ
• Description: IC ADC 24BIT 2CH W/PGA 24-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7192BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119)
• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 24bit
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analogue: 3V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Supply: RoHS Compliant
• Sampling Rate: 4.8kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7192
The sinc
120 dB, assuming a stable master clock, and the sinc
a rejection of 100 dB. The stop-band attenuation is, typically,
53 dB for the sinc
The 3 dB frequency for the sinc
and for the sinc
Chop Enabled
With chop enabled, the ADC offset and offset drift are
minimized. When chop is enabled, the analog input pins are
continuously swapped. Therefore, with the analog input pins
connected in one direction, the settling time of the sinc filter is
allowed to elapse until a valid conversion is available. The analog
input pins are then inverted, and another valid conversion is
obtained. Subsequent conversions are then averaged so that the
offset is minimized. This continuous swapping of the analog
input pins and the averaging of subsequent conversions means
that the offset drift is also minimized.
Chopping affects the output data rate and settling time of the
ADC. For sinc
For sinc
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
ADC
CLK
= master clock (4.92 MHz nominal).
is the output data rate.
f
f
f
f
–100
3dB
3dB
ADC
ADC
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
3
= 0.23 × f
= 0.272 × f
Figure 20. Sinc
4
, the output data rate is equal to
= f
= f
0
filter provides 50 Hz (±1 Hz) rejection in excess of
CLK
CLK
/(4 × 1024 × FS[9:0])
/(3 × 1024 × FS[9:0])
4
, the output data rate is equal to
3
25
filter, the 3 dB frequency is equal to
4
ADC
filter but equal to 40 dB for the sinc
ADC
3
Filter Response (50 Hz Output Data Rate)
50
FREQUENCY (Hz)
4
75
filter is equal to
100
125
3
filter gives
3
filter.
150
Rev. A | Page 26 of 40
The value of FS[9:0] can be varied from 1 to 1023. This results
in an output data rate of 1.173 Hz to 1200 Hz for the sinc
and 1.56 Hz to 1600 Hz for the sinc
sinc
Therefore, with chop enabled, the settling time is reduced for a
given output data rate compared to the chop disabled mode.
However, for a given FS[9:0] value, the output data rate is less
with chop enabled when compared with the chop disabled
mode. For either the sinc
equal to
Figure 21 and Figure 22 show the filter response for the sinc
filter and sinc
shown in the plots, the stop-band attenuation is less when
compared with the chop disabled modes.
Figure 22. Sinc
Figure 21. Sinc
3
t
f
or sinc
SETTLE
3dB
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
= 0.24 × f
0
0
= 2/f
4
3
4
is equal to
3
Filter Response (Output Data Rate =12.5 Hz, Chop Enabled)
Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled)
filter, respectively, when chop is enabled. As
ADC
25
25
ADC
3
50
50
or sinc
FREQUENCY (Hz)
FREQUENCY (Hz)
4
75
75
filter, the cutoff frequency f
3
filter. The settling time for
100
100
125
125
150
150
4
filter
3dB
4
is