MC13892JVLR2 Freescale, MC13892JVLR2 Datasheet - Page 65

• Manufacturer Part Number: MC13892JVLR2
• Manufacturer: Freescale

Specifications of MC13892JVLR2

• Operating Temperature (max): 85C
• Operating Temperature (min): -30C
• Mounting: Surface Mount
• Package Type: BGA
• Case Length: 12mm
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Compliant

POWER SAVING
SYSTEM STANDBY
further activity is detected, or if a gaming interface sits idle for an extended period. Two Standby pins are provided for board level
control of timing in and out of such deep sleep modes.
disabling some regulators, or forcing some GPO low. This can be obtained by SPI configuration of the Standby response of the
circuits along with control of the Standby pins.
the STANDBY and the STANDBYSEC are activated. The states of the Standby pins only have influence in On mode. A command
to transition to one of the Low Power Off states (User Off or Memory Hold, initiated with USEROFFSPI = 1) has priority over
Standby.
take into account the programmed input polarities associated with each pin.
actually going into standby (i.e. before turning off some supplies). No delay is applied when coming out of standby.
REGULATOR MODE CONTROL
scheme, thus, there are no distinct operating modes such as a Normal mode and a Low Power mode. Therefore, no specific
control is required to put these regulators in a Low Power mode.
mode. However, since a load current detection cannot be performed for these regulators, the transition between both modes is
not automatic and is controlled by setting the corresponding mode bits for the operational behavior desired.
in
the VxMODE bit for the specific regulator. Therefore, depending on the configuration selected, the automatic Low Power mode
is available.
previously. Each regulator and GPO has an associated SPI bit for this. When the bit is not set, STANDBY is of no influence. The
actual operating mode of the regulators as a function of STANDBY is not reflected through the SPI. In other words, the SPI will
read back what is programmed, not the actual state.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 30. Standby Pin and Polarity Control
Notes
46.
STANDBY (Pin)
Power Control
A product may be designed to go into DSM after periods of inactivity, such as if a music player completes a play list and no
When a product is in DSM it may be able to reduce the overall platform current by lowering the switcher output voltage,
To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both
Note that the Standby pins are programmable for Active High or Active Low polarity, and that decoding of a Standby event will
When requesting standby, a programmable delay (STBYDLY) of 0 to 3 clock cycles of the 32 kHz clock is applied before
The regulators with embedded pass devices (VDIG, VPLL, VIOHI, VUSB, VUSB2, and VAUDIO) have an adaptive biasing
The regulators with external pass devices (VSD, VVIDEO, VGEN1, and VGEN2) can also operate in a Normal and Low Power
The regulators VGEN3 and VCAM can be configured for using the internal pass device or external pass device as explained
The regulators can be disabled and the general purpose outputs can be forced low when going into Standby as described
STANDBY = 0: System is not in Standby; STANDBY = 1: System is in Standby and Standby programmability is activated.
0
x
1
x
0
0
1
1
System. For both configurations, the transition between Normal and Low Power modes is controlled by setting
Table 31. Delay of STANDBY- Initiated Response
STANDBYINV (SPI bit)
STBYDLY[1:0]
0
x
1
x
1
1
0
0
00
01
10
11
STANDBYSEC (Pin)
No Delay
One 32 K period (default)
Two 32 K periods
Three 32 K periods
x
0
x
1
0
1
0
1
Function (1)
STANDBYSECINV (SPI bit)
x
0
x
1
1
0
1
0
FUNCTIONAL DEVICE OPERATION
STANDBY Control
OPERATING MODES
0
0
0
0
1
1
1
1
(46)
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